* fix l2l fwd

* fix l2l fwd mask

* fix s0_l2l_fwd_valid

* fix l2l fwd mask and fuOpType logic

* fix l2l fwd cancel logic

* add  fuOpType fast path

* remove useless variable

* fix s1_addr_misaligned

* fix l2l_fwd_out.data

Prefix the port signal name of memblock to indicate the direction and source.

* PTW: Move PTW to MemBlock

Move itlbrepeater to Frontend and MemBlock, dtlbrepeater to MemBlock,
L2 TLB (PTW) and ptw_to_l2_buffer to Memblock for better partition.

* MMU: Fix sfence delay to synchronize modules

* add new ldu and stu

* add fast replay kill at s1

* fix pointer chasing cancel

* pick flushpipe_rvc

* merge flushpipe_rvc

* fix s3_cache_rep and s3_feedbacked

* fix fast replay condition

---------
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> decode -> rename -> dispatch

* top-down: add dummy connections

* top-down: update TopdownCounters

* top-down: imp backend analysis and counter dump

* top-down: add HartId in `addSource`

* top-down: broadcast lqIdx of ROB head

* top-down: frontend signal done

* top-down: add memblock topdown interface

* Bump HuanCun: add TopDownMonitor

* top-down: receive and handle reasons in dispatch

* top-down: remove previous top-down code

* TopDown: add MemReqSource enum

* TopDown: extend mshr_latency range

* TopDown: add basic Req Source

TODO: distinguish prefetch

* dcache: distinguish L1DataPrefetch and CPUData

* top-down: comment out debugging perf counters in ibuffer

* TopDown: add path to pass MemReqSource to HuanCun

* TopDown: use simpler logic to count reqSource and update Probe count

* frontend: update topdown counters

* Update HuanCun Topdown for MemReqSource

* top-down: fix load stalls

* top-down: Change the priority of different stall reasons

* top-down: breakdown OtherCoreStall

* sbuffer: fix eviction

* when valid count reaches StoreBufferSize, do eviction

* sbuffer: fix replaceIdx

* If the way selected by the replacement algorithm cannot be written into dcache, its result is not used.

* dcache, ldu: fix vaddr in missqueue

This commit prevents the high bits of the virtual address from being truncated

* fix-ldst_pri-230506

* mainpipe: fix loadsAreComing

* top-down: disable dedup

* top-down: remove old top-down config

* top-down: split lq addr from ls_debug

* top-down: purge previous top-down code

* top-down: add debug_vaddr in LoadQueueReplay

* add source rob_head_other_repay

* remove load_l1_cache_stall_with/wihtou_bank_conflict

* dcache: split CPUData & refill latency

* split CPUData to CPUStoreData & CPULoadData & CPUAtomicData
* monitor refill latency for all type of req

* dcache: fix perfcounter in mq

* io.req.bits.cancel should be applied when counting req.fire

* TopDown: add TopDown for CPL2 in XiangShan

* top-down: add hartid params to L2Cache

* top-down: fix dispatch queue bound

* top-down: no DqStall when robFull

* topdown: buspmu support latency statistic (#2106)

* perf: add buspmu between L2 and L3, support name argument

* bump difftest

* perf: busmonitor supports latency stat

* config: fix cpl2 compatible problem

* bump utility

* bump coupledL2

* bump huancun

* misc: adapt to utility key&field

* config: fix key&field source, remove deprecated argument

* buspmu: remove debug print

* bump coupledl2&huancun

* top-down: fix sq full condition

* top-down: classify "lq full" load bound

* top-down: bump submodules

* bump coupledL2: fix reqSource in data path

* bump coupledL2

---------
Co-authored-by: Ntastynoob <934348725@qq.com>
Co-authored-by: NGuokai Chen <chenguokai17@mails.ucas.ac.cn>
Co-authored-by: Nlixin <1037997956@qq.com>
Co-authored-by: NXiChen <chenxi171@mails.ucas.ac.cn>
Co-authored-by: NZhou Yaoyang <shinezyy@qq.com>
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>
Co-authored-by: Nwakafa <wangkaifan@ict.ac.cn>

* hint: add CustomHint interface

* dcache: fix replacement & mshrId update

* access replacement only once per load
* update mshrId in replayqueue only when this load enters mshr

* replay: block cache miss load

* block cache miss load until hint or dcache refill appears

* buffer: fix hint buffer depth to 1

* ldu: add dcache miss l2hint fast replay path

* bump coupledL2

* bump utility

---------
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>
Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>

BREAKING CHANGE: new LSU/LQ architecture introduced in this PR

In this commit, we replace unified LQ with:
* virtual load queue
* load replay queue
* load rar queue
* load raw queue
* uncache buffer

It will provide larger ooo load window.

NOTE: IPC loss in this commit is caused by MDP problems, for previous MDP
does not fit new LSU architecture. 
MDP update is not included in this commit, IPC loss will be fixed by MDP update later.

---------
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>

Besides adding load/store arch database, this PR also fixed a bug which caused
prefetch using l1 info failed to work.

Former RTL change break `isFirstIssue` flag gen logic, which caused prefetcher
failed to receive prefetch train info from L1. This commit should fix that.

* ROB: add inst db drop

globalID signal output is still duplicated

* TLB: TLB will carry mem idx when req and resp

* InstDB: update the TLBFirstIssue

* InstDB: the first version is complete

* InstDB: update decode logic

* InstDB: update ctrlBlock writeback

* Merge: fix bug

* merge: fix compile bug

* code rule: rename debug signals and add db's FPGA signal control

* code rule: update db's FPGA signal control

* ldu: fix isFirstIssue flag for ldflow from rs

* ldu: isFirstIssue flag for hw pf is always false

---------
Co-authored-by: Ngood-circle <fenghaoyuan19@mails.ucas.ac.cn>
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

This commit changes the reset of all modules to asynchronous style,
including changes on the initialization values of some registers.
For async registers, they must have constant reset values.

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

* L2TLB: Fix a bug of Prefetcher

* MMU: Add ChiselDB

* MMU: Add Fake PTW

* MMU: Fix ChiselDB for dual core

* top-down: add initial top-down features

* rob600: enlarge queue/buffer size

* 🎨 After git pull

* ✨ Add BranchResteers->CtrlBlock

* ✨ Cg BranchResteers after pending

* ✨ Add robflush_bubble & ldReplay_bubble

* 🚑 Fix loadReplay->loadReplay.valid

* 🎨 Dlt printf

* ✨ Add stage2_redirect_cycles->CtrlBlock

* :saprkles: CtrlBlock:Add s2Redirect_when_pending

* ✨ ID:Add ifu2id_allNO_cycle

* ✨ Add ifu2ibuffer_validCnt

* ✨ Add ibuffer_IDWidth_hvButNotFull

* ✨ Fix ifu2ibuffer_validCnt

* 🚑 Fix ibuffer_IDWidth_hvButNotFull

* ✨ Fix ifu2ibuffer_validCnt->stop

* feat(buggy): parameterize load/store pipeline, etc.

* fix: use LoadPipelineWidth rather than LoadQueueSize

* fix: parameterize `rdataPtrExtNext`

* fix(SBuffer): fix idx update logic

* fix(Sbuffer): use `&&` to generate flushMask instead of `||`

* fix(atomic): parameterize atomic logic in `MemBlock`

* fix(StoreQueue): update allow enque requirement

* chore: update comments, requirements and assertions

* chore: refactor some Mux to meet original logic

* feat: reduce `LsMaxRsDeq` to 2 and delete it

* feat: support one load/store pipeline

* feat: parameterize `EnsbufferWidth`

* chore: resharp codes for better generated name

* top-down: add initial top-down features

* rob600: enlarge queue/buffer size

* top-down: add l1, l2, l3 and ddr loads bound perf counters

* top-down: dig into l1d loads bound

* top-down: move memory related counters to `Scheduler`

* top-down: add 2 Ldus and 2 Stus

* top-down: v1.0

* huancun: bump HuanCun to a version with top-down

* chore: restore parameters and update `build.sc`

* top-down: use ExcitingUtils instead of BoringUtils

* top-down: add switch of top-down counters

* top-down: add top-down scripts

* difftest: enlarge stuck limit cycles again
Co-authored-by: Ngaozeyu <gaozeyu18@mails.ucas.ac.cn>

* freelist & refcounter: implement arch states

* walk: restore and walk again when redirecting

* ROB: optimize invalidation of `valid`

Now we update data field (fwd data, uop) in load queue when load_s2
is valid. It will help to on lq wen fanout problem.

State flags will be treated differently. They are still updated
accurately according to loadIn.valid
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

Move imm addition to stage 0.

each tlb's port can be configured to be block or non-blocked.
For blocked port, there will be a req miss slot stored in tlb, but belong to
core pipeline, which means only core pipeline flush will invalid them.

For another, itlb also use PTW Filter but with only 4 entries.
Last, keep svinval extension as usual, still work.


* tlb: add blocked-tlb support, miss frontend changes

* tlb: remove tlb's sameCycle support, result will return at next cycle

* tlb: remove param ShouldBlock, move block method into TLB module

* tlb: fix handle_block's miss_req logic

* mmu.filter: change filter's req.ready to canEnqueue

when filter can't let all the req enqueue, set the req.ready to false.
canEnqueue after filtering has long latency, so we use **_fake
without filtering, but the filter will still receive the reqs if
it can(after filtering).

* mmu.tlb: change name from BTlbPtwIO to VectorTlbPtwIO

* mmu: replace itlb's repeater to filter&repeaternb

* mmu.tlb: add TlbStorageWrapper to make TLB cleaner

more: BlockTlbRequestorIO is same with TlbRequestorIO, rm it

* mmu.tlb: rm unused param in function r_req_apply, fix syntax bug

* [WIP]icache: itlb usage from non-blocked to blocked

* mmu.tlb: change parameter NBWidth to Seq of boolean

* icache.mainpipe: fix itlb's resp.ready, not always true

* mmu.tlb: add kill sigal to blocked req that needs sync but fail

in frontend, icache,itlb,next pipe may not able to sync.
blocked tlb will store miss req ang blocks req, which makes itlb
couldn't work. So add kill logic to let itlb not to store reqs.

One more thing: fix icache's blocked tlb handling logic

* icache.mainpipe: fix tlb's ready_recv logic

icache mainpipe has two ports, but these two ports may not valid
all the same time. So add new signals tlb_need_recv to record whether
stage s1 should wait for the tlb.

* tlb: when flush, just set resp.valid and pf, pf for don't use it

* tlb: flush should concern satp.changed(for blocked io now)

* mmu.tlb: add new flush that doesn't flush reqs

Sfence.vma will flush inflight reqs and flushPipe
But some other sfence(svinval...) will not. So add new flush to
distinguish these two kinds of sfence signal

morw: forget to assign resp result when ptw back, fix it

* mmu.tlb: beautify miss_req_v and miss_v relative logic

* mmu.tlb: fix bug, when ptw back and bypass, concern level to genPPN

bug: when ptw back and bypass, forgot to concern level(1GB/2MB/4KB)
when genPPN.

by the way: some funtions need ": Unit = ", add it.

* mmu.filter: fix bug of canEnqueue, mixed with tlb_req and tlb.req

* icache.mainpipe: fix bug of tlbExcp's usage, & with tlb_need_back

Icache's mainpipe has two ports, but may only port 0 is valid.
When a port is invalid, the tlbexcp should be false.(Actually, should
be ignored).
So & tlb_need_back to fix this bug.

* sfence: instr in svinval ext will also flush pipe

A difficult problem to handle:
Sfence and Svinval will flush MMU, but only Sfence(some svinval)
  will flush pipe. For itlb that some requestors are blocked and
  icache doesn't recv flush for simplicity, itlb's blocked ptw req
  should not be flushed.
It's a huge problem for MMU to handle for good or bad solutions. But
  svinval is seldom used, so disable it's effiency.

* mmu: add parameter to control mmu's sfence delay latency

Difficult problem:
  itlb's blocked req should not be abandoned, but sfence will flush
  all infight reqs. when itlb and itlb repeater's delay is not same(itlb
  is flushed, two cycles later, itlb repeater is flushed, then itlb's
  ptw req after flushing will be also flushed sliently.
So add one parameter to control the flush delay to be the same.

* mmu.tlb: fix bug of csr.priv's delay & sfence valid when req fire

1. csr.priv's delay
csr.priv should not be delayed, csr.satp should be delayed.
for excep/intr will change csr.priv, which will be changed at one
instruction's (commit?). but csrrw satp will not, so satp has more
cycles to delay.
2. sfence
when sfence valid but blocked req fire, resp should still fire.
3. satp in TlbCsrBundle
let high bits of satp.ppn to be 0.U

* tlb&icache.mainpipe: rm commented codes

* mmu: move method genPPN to entry bundle

* l1tlb: divide l1tlb flush into flush_mmu and flush_pipe

Problem:
For l1tlb, there are blocked and non-blocked req ports.
For blocked ports, there are req slots to store missed reqs.
Some mmu flush like Sfence should not flush miss slots for outside
may still need get tlb resp, no matter wrong and correct resp.
For example. sfence will flush mmu and flush pipe, but won't flush
reqs inside icache, which waiting for tlb resp.
For example, svinval instr will flush mmu, but not flush pipe. so
tlb should return correct resp, althrough the ptw req is flushed
when tlb miss.

Solution:
divide l1tlb flush into flush_mmu and flush_pipe.
The req slot is considered to be a part of core pipeline and should
only be flushed by flush_pipe.
flush_mmu will flush mmu entries and inflight ptw reqs.
When miss but sfence flushed its ptw req, re-send.

* l1tlb: code clean, correct comments and rm unused codes

* l2tlb: divide filterSize into ifiterSize and dfilterSize

* l2tlb: prefetch req won't enter miss queue. Rename MSHR to missqueue

* l1tlb: when disable vm, ptw back should not bypass tlb and should let miss req go ahead

* ctrl: copy dispatch2 to avoid cross-module loops

This commit makes copies of dispatch2 in CtrlBlock to avoid long
cross-module timing loop paths. Should be good for timing.

* dpq: re-write queue read logic

This commit adds a Reg-Vec to store the queue read data. Since
most queues read at most the current numRead and the next numRead
entries, the read timing can be optimized by reading the data one
cycle earlier.

This commit re-pipelines ECC check logic in data cache and exception generate logic for better timing.
Now ecc error is checked 1 cycle after reading result from data sram. An extra cycle is added for load
writeback to ROB.

Future work: move the pipeline to https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/backend/CtrlBlock.scala#L266-L277, which add a regnext.

* dcache: repipeline ecc check logic for timing

* chore: fix normal loadAccessFault logic

* wbu: delay load unit wb for 1 cycle

* dcache: add 1 extra cycle for beu error report

* feat: parameterize load/store pipeline, etc.

* fix: use LoadPipelineWidth rather than LoadQueueSize

* fix: parameterize `rdataPtrExtNext`

* SBuffer: fix idx update logic

* atomic: parameterize atomic logic in `MemBlock`

* StoreQueue: update allow enque requirement

* feat: support one load/store pipeline

* feat: parameterize `EnsbufferWidth`

* chore: resharp codes for better generated name

This commit fixes the implementation of WFI. The WFI instruction
waits in the ROB until an interrupt might need servicing.

According to the RISC-V manual, the WFI must be unaffected by the
global interrupt bits in `mstatus` and the delegation register
`mideleg`.

The RISC-V WFI instruction is previously decoded as NOP. This commit
adds support for the real wait-for-interrupt (WFI).

We add a state_wfi FSM in the ROB. After WFI leaves the ROB, the next
instruction will wait in the ROB until an interrupt.

old missqueue: cache req miss slot and mem access-er
Problem: these two func are totally different, make mq hard to handle in a single select policy.
Solution: divide these two funciton into two module.
  new MissQueue: only hold reqs that page cache miss and need re-req cache， a simple flushable queue
  llptw: Last level ptw, only access ptes, priorityMux queue

* mmu: rename PTW.scala to L2TLB.scala

* mmu: rename PTW to L2TLB

* mmu: rename PtwFsm to PTW

* mmu.l2tlb: divide missqueue into 'missqueue' and llptw

old missqueue: cache req miss slot and mem access-er
Problem: these two func are totally different, make mq hard to handle
  in single select policy.
Solution: divide these two funciton into two module.
  new MissQueue: only hold reqs that page cache miss and new re-req
  cache
  llptw: Last level ptw, only access ptes

* mmu.l2tlb: syntax bug that misses io assign

* mmu.l2tlb: fix bug that mistakes ptw's block signal

* Adjusted reset signals

* Support reset tree

* mem: fix error csr update

* dcache: l2 error will now trigger atom error

* chore: fix cache error debug decoder

* mem: split L1CacheErrorInfo and L1BusErrorUnitInfo

This commit adds an LsqEnqCtrl module to add one more clock cycle
between dispatch and load/store queue.

LsqEnqCtrl maintains the lqEnqPtr/sqEnqPtr and lqCounter/sqCounter.
They are used to determine whether load/store queue can accept new
instructions. After that, instructions are sent to load/store queue.
This module decouples queue allocation and real enqueue.

Besides, uop storage in load/store queue are optimized. In dispatch,
only robIdx is required. Other information is naturally conveyed in
the pipeline and can be stored later in load/store queue if needed.
For example, exception vector, trigger, ftqIdx, pdest, etc are
unnecessary before the instruction leaves the load/store pipeline.

* mem,cacheop: fix read data writeback

* mem,cacheop: rename cacheop state bits

These bits are different from w_*, s_* bits in cache

* mem: enable icache op feedback

* icache: update cache op implementation

* chore: remove cache op logic from XSCore.scala

This commit optimizes the coding style and timing for hardware
performance counters.

By default, performance counters are RegNext(RegNext(_)).

This commit adds WritebackSink and WritebackSource parameters for
multiple modules. These traits hide implementation details from
other modules by defining IO-related functions in modules.

By using WritebackSink, ROB is able to choose the writeback sources.
Now fflags and exceptions are connected from exe units to reduce write
ports and optimize timing.

Further optimizations on write-back to RS and better coding style to
be added later.

* SoC: add axi4spliter

* pmp: add apply method to reduce loc

* pma: add PMA used in axi4's spliter

* Fix package import

* pma: re-write tl-pma, put tl-pma into AXI4Spliter

* pma: add memory mapped pma

* soc: rm dma port, rm axi4spliter, mv mmpma out of spliter

* Remove unused files

* update dma pma check port at SimTop.scala; update pll lock defalt value to 1
Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
Co-authored-by: Nrvcoresjw <shangjiawei@rvcore.com>

* FDivSqrt: use hierarchy API to avoid dedup bug

* Dedup: use hartId from io port instead of core parameters

* Bump fudian