sms: prefetch to l1

src/main/scala/xiangshan/XSCore.scala

@@ -366,12 +366,6 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
   XSPerfHistogram("fastIn_count", PopCount(allFastUop1.map(_.valid)), true.B, 0, allFastUop1.length, 1)
   XSPerfHistogram("wakeup_count", PopCount(rfWriteback.map(_.valid)), true.B, 0, rfWriteback.length, 1)
 
-  // l1 prefetch fuzzer, for debug only
-  val debug_l1PrefetchFuzzer = Module(new L1PrefetchFuzzer)
-  debug_l1PrefetchFuzzer.io.req <> memBlock.io.prefetch_req
-  debug_l1PrefetchFuzzer.io.vaddr := memBlock.io.writeback(0).bits.debug.vaddr
-  debug_l1PrefetchFuzzer.io.paddr := memBlock.io.writeback(0).bits.debug.paddr
-
   ctrlBlock.perfinfo.perfEventsEu0 := exuBlocks(0).getPerf.dropRight(outer.exuBlocks(0).scheduler.numRs)
   ctrlBlock.perfinfo.perfEventsEu1 := exuBlocks(1).getPerf.dropRight(outer.exuBlocks(1).scheduler.numRs)
   if (!coreParams.softPTW) {

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -140,6 +140,7 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
   val stdExeUnits = Seq.fill(exuParameters.StuCnt)(Module(new StdExeUnit))
   val stData = stdExeUnits.map(_.io.out)
   val exeUnits = loadUnits ++ storeUnits
+  val l1_pf_req = Wire(Decoupled(new L1PrefetchReq()))
   val prefetcherOpt: Option[BasePrefecher] = coreParams.prefetcher.map {
     case _: SMSParams =>
       val sms = Module(new SMSPrefetcher())
@@ -156,6 +157,12 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
     outer.pf_sender_opt.get.out.head._1.l2_pf_en := RegNextN(io.csrCtrl.l2_pf_enable, 2, Some(true.B))
     pf.io.enable := RegNextN(io.csrCtrl.l1D_pf_enable, 2, Some(false.B))
   })
+  prefetcherOpt match {
+    case Some(pf) => l1_pf_req <> pf.io.l1_req
+    case None =>
+      l1_pf_req.valid := false.B
+      l1_pf_req.bits := DontCare
+  }
   val pf_train_on_hit = RegNextN(io.csrCtrl.l1D_pf_train_on_hit, 2, Some(true.B))
 
   loadUnits.zipWithIndex.map(x => x._1.suggestName("LoadUnit_"+x._2))
@@ -186,14 +193,14 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
   val stOut = io.writeback.drop(exuParameters.LduCnt).dropRight(exuParameters.StuCnt)
 
   // prefetch to l1 req
-  loadUnits.map(load_unit => {
-    load_unit.io.prefetch_req.valid <> io.prefetch_req.valid
-    load_unit.io.prefetch_req.bits <> io.prefetch_req.bits
+  loadUnits.foreach(load_unit => {
+    load_unit.io.prefetch_req.valid <> l1_pf_req.valid
+    load_unit.io.prefetch_req.bits <> l1_pf_req.bits
   })
   // when loadUnits(0) stage 0 is busy, hw prefetch will never use that pipeline
   loadUnits(0).io.prefetch_req.bits.confidence := 0.U
 
-  io.prefetch_req.ready := (io.prefetch_req.bits.confidence > 0.U) ||
+  l1_pf_req.ready := (l1_pf_req.bits.confidence > 0.U) ||
     loadUnits.map(!_.io.ldin.valid).reduce(_ || _)
 
   // TODO: fast load wakeup

src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala

@@ -5,12 +5,13 @@ import chisel3.util._
 import chipsalliance.rocketchip.config.Parameters
 import xiangshan._
 import xiangshan.cache.mmu.TlbRequestIO
-import xiangshan.mem.LsPipelineBundle
+import xiangshan.mem.{L1PrefetchReq, LsPipelineBundle}
 
 class PrefetcherIO()(implicit p: Parameters) extends XSBundle {
   val ld_in = Flipped(Vec(exuParameters.LduCnt, ValidIO(new LsPipelineBundle())))
   val tlb_req = new TlbRequestIO(nRespDups = 2)
   val pf_addr = ValidIO(UInt(PAddrBits.W))
+  val l1_req = DecoupledIO(new L1PrefetchReq())
   val enable = Input(Bool())
 }