- 01 6月, 2020 1 次提交
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由 LinJiawei 提交于
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- 10 5月, 2020 3 次提交
- 09 5月, 2020 1 次提交
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由 LinJiawei 提交于
[IntToFloat]: Count leading zeros of positive and negative number in parallel because IntToFloat is in the critical path
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- 08 5月, 2020 1 次提交
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由 LinJiawei 提交于
FPUv0.1 can pass all rvf/rvd tests in both riscv-tests and berkeley-softfloat Signed-off-by: NLinJiawei <linjiav@outlook.com>
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- 24 12月, 2019 3 次提交
- 17 12月, 2019 2 次提交
- 14 12月, 2019 5 次提交
- 13 12月, 2019 2 次提交
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由 William Wang 提交于
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由 William Wang 提交于
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- 11 12月, 2019 19 次提交
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由 Zihao Yu 提交于
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由 William Wang 提交于
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由 William Wang 提交于
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由 William Wang 提交于
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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由 William Wang 提交于
* According to The RISC-V Instruction Set Manual Volume II: Privileged Architecture, for instruction-fetch access or page-fault exceptions on systems with variable-length instructions, m/stval will contain the virtual address of the portion of the instruction that caused the fault while m/sepc will point to the beginning of the instruction.
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由 Zihao Yu 提交于
* To run more programs on debian, we use 256MB memory described in dts. But if the hardware still provides 128MB memory, the memory access will wrap around when Linux allocate a physical page excceed 128MB, which causes wrong memory access.
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由 Zihao Yu 提交于
* after 4 hours, the command will be sent repeatly
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
* An instruciton fetch will set the A bit of the PTE, even this instruction will be flushed later due to branch mis-prediction. Although this will not cause correctness issue, it will introduce inconsistent behavior compared with NEMU. * To run DiffTest while testing debian, a solution is to disable updating A bit and D bit in both NOOP and NEMU.
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
* this can reduce the idle time in Linux
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由 Zihao Yu 提交于
* this is because we can not control the mip.mtip bit in NEMU
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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- 09 12月, 2019 3 次提交
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由 Zihao Yu 提交于
* This will skip instruction fetching from MMIO, which is hard to compare with NEMU.
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由 Zihao Yu 提交于
* IFU will send 64-bit fetch requests. Originally flash will only response with rdata = 0x00000000????????. For instrucitons aligned at 4-byte address, IDU will select 0x00000000 as the target instruction. * To fix this, we let flash reponse with 2 copies. * Note that RVC instruction stream like 0xccbbbbbbbbaa in flash can not be handled correctly. The current solution only support non-RVC code in flash.
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由 Zihao Yu 提交于
* NOTE: if we fetch and execute a store instruction from MMIO, currently DiffTest can not handle this situation.
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