This reverts commit e100a73b.

Now, they are still 64bit(negotiated by diplomacy), since AXI4RAM is 64bit wide.
Considering changing AXI4RAM to 64bit.

to allow more flexible address range configuration.
With only one AddressSet, we can not even represent
very simple address ranges like [2G, 32G).

For chiselTest peek/poke, if some output signal is combinationally
dependent of some input signal, you can peek the latest output value
right after poke input value.

So, to determine fire or not, we can simply peek valid and ready at the
same time. If we peek ready later to determine fire, we may get the
wrong ready value.

First, we populate L2 with random data through dcache.
Then we use cache control instructions to flush the entire L2.
Then we get with L1plus, and see what happens.

to allow more flexible testbench.