AXI4SlaveModule: use Seq[AddressSet] instead of AddressSet

to allow more flexible address range configuration.
With only one AddressSet, we can not even represent
very simple address ranges like [2G, 32G).

src/main/scala/device/AXI4DummySD.scala

@@ -53,7 +53,7 @@ class SDHelper extends BlackBox with HasBlackBoxInline {
 
 class AXI4DummySD
 (
-  address: AddressSet
+  address: Seq[AddressSet]
 )(implicit p: Parameters)
   extends AXI4SlaveModule(address, executable = false) with HasSDConst
 {

src/main/scala/device/AXI4Flash.scala

@@ -8,7 +8,7 @@ import utils._
 
 class AXI4Flash
 (
-  address: AddressSet
+  address: Seq[AddressSet]
 )(implicit p: Parameters)
   extends AXI4SlaveModule(address, executable = false)
 {

src/main/scala/device/AXI4Keyboard.scala

@@ -14,7 +14,7 @@ class KeyboardIO extends Bundle {
 // this Module is not tested
 class AXI4Keyboard
 (
-  address: AddressSet
+  address: Seq[AddressSet]
 )(implicit p: Parameters)
   extends AXI4SlaveModule(address, executable = false, _extra = new KeyboardIO)
 {

src/main/scala/device/AXI4RAM.scala

@@ -20,7 +20,7 @@ class RAMHelper(memByte: BigInt) extends BlackBox with HasXSParameter {
 
 class AXI4RAM
 (
-  address: AddressSet,
+  address: Seq[AddressSet],
   memByte: Long,
   useBlackBox: Boolean = false,
   executable: Boolean = true,

src/main/scala/device/AXI4SlaveModule.scala

@@ -10,7 +10,7 @@ import xiangshan.HasXSLog
 
 abstract class AXI4SlaveModule[T <: Data]
 (
-  address: AddressSet,
+  address: Seq[AddressSet],
   executable: Boolean = true,
   beatBytes: Int = 8,
   burstLen: Int = 1,
@@ -19,7 +19,7 @@ abstract class AXI4SlaveModule[T <: Data]
 
   val node = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
     Seq(AXI4SlaveParameters(
-      Seq(address),
+      address,
       regionType = RegionType.UNCACHED,
       executable = executable,
       supportsWrite = TransferSizes(1, beatBytes * burstLen),

src/main/scala/device/AXI4Timer.scala

@@ -12,7 +12,7 @@ class TimerIO extends Bundle {
 class AXI4Timer
 (
   sim: Boolean = false,
-  address: AddressSet
+  address: Seq[AddressSet]
 )(implicit p: Parameters)
   extends AXI4SlaveModule(address, executable = false, _extra = new TimerIO)
 {

src/main/scala/device/AXI4UART.scala

@@ -20,7 +20,7 @@ class UARTIO extends Bundle {
 
 class AXI4UART
 (
-  address: AddressSet
+  address: Seq[AddressSet]
 )(implicit p: Parameters)
   extends AXI4SlaveModule(address, executable = false, _extra = new UARTIO)
 {

src/main/scala/device/AXI4VGA.scala

@@ -54,7 +54,7 @@ class VGACtrlBundle extends Bundle {
 
 class VGACtrl
 (
-  address: AddressSet
+  address: Seq[AddressSet]
 )(implicit p: Parameters)
   extends AXI4SlaveModule(address, _extra = new VGACtrlBundle, executable = false) with HasVGAParameter {
   override lazy val module = new AXI4SlaveModuleImp[VGACtrlBundle](this) {
@@ -106,8 +106,8 @@ class FBHelper extends BlackBox with HasBlackBoxInline {
 class AXI4VGA
 (
   sim: Boolean = false,
-  fbAddress: AddressSet,
-  ctrlAddress: AddressSet
+  fbAddress: Seq[AddressSet],
+  ctrlAddress: Seq[AddressSet]
 )(implicit p: Parameters)
   extends LazyModule with HasVGAParameter {
 

src/test/scala/cache/L1plusCacheTest.scala

@@ -50,7 +50,7 @@ class L1plusTestTop()(implicit p: Parameters) extends LazyModule{
   ))
 
   val ram = LazyModule(new AXI4RAM(
-    AddressSet(0x0L, 0xffffffffffL),
+    Seq(AddressSet(0x0L, 0xffffffffffL)),
     memByte = 128 * 1024 * 1024,
     useBlackBox = false
   ))

src/test/scala/cache/L2CacheNonInclusiveGetTest.scala

@@ -51,7 +51,7 @@ class L2NonInclusiveGetTestTop()(implicit p: Parameters) extends LazyModule {
       beatBytes = 8))))
 
   val ram = LazyModule(new AXI4RAM(
-    AddressSet(0x0L, 0x7ffffffL),
+    Seq(AddressSet(0x0L, 0x7ffffffL)),
     memByte = 128 * 1024 * 1024,
     useBlackBox = false
   ))

src/test/scala/cache/L2CacheTest.scala

@@ -100,7 +100,7 @@ class L2TestTop()(implicit p: Parameters) extends LazyModule{
   ))
 
   val ram = LazyModule(new AXI4RAM(
-    AddressSet(0x0L, 0xffffffffffL),
+    Seq(AddressSet(0x0L, 0xffffffffffL)),
     memByte = 128 * 1024 * 1024,
     useBlackBox = false
   ))

src/test/scala/device/AXI4RamTest.scala

@@ -19,7 +19,7 @@ class AXI4RamFuzzTest()(implicit p: Parameters) extends LazyModule {
     inFlight = 10
   ))
   val ident = LazyModule(new DebugIdentityNode())
-  val axiRam = LazyModule(new AXI4RAM(addressSet, memByte = 1024))
+  val axiRam = LazyModule(new AXI4RAM(Seq(addressSet), memByte = 1024))
 
   axiRam.node :=
     AXI4UserYanker() :=
@@ -38,7 +38,7 @@ class AXI4RamBurstTest()(implicit p: Parameters) extends LazyModule {
 
   val addressSet = AddressSet(0x38000000L, 0x0000ffffL)
   val burst = LazyModule(new AXI4BurstMaster(startAddr = addressSet.base.toLong, nOp = 3))
-  val axiRam = LazyModule(new AXI4RAM(addressSet, memByte = 1024))
+  val axiRam = LazyModule(new AXI4RAM(Seq(addressSet), memByte = 1024))
 
   axiRam.node := burst.node
 
@@ -55,7 +55,7 @@ class AXI4RamTLBurstTest()(implicit p: Parameters) extends LazyModule {
 
   val tlburst = LazyModule(new TLBurstMaster(startAddr = addressSet.base.toLong, nOp = 1, burstLen = 32))
   val ident = LazyModule(new DebugIdentityNode())
-  val axiRam = LazyModule(new AXI4RAM(addressSet, memByte = 1024))
+  val axiRam = LazyModule(new AXI4RAM(Seq(addressSet), memByte = 1024))
 
   axiRam.node :=
     AXI4UserYanker() :=

src/test/scala/device/AXI4TimerTest.scala

@@ -15,7 +15,7 @@ class AXI4TimerTestTop(implicit p: Parameters) extends LazyModule {
   val addressSet = AddressSet(0x38000000L, 0x0000ffffL)
   val fuzz = LazyModule(new TLFuzzer(nOperations = 10, overrideAddress = Some(addressSet), inFlight = 1))
   val ident = LazyModule(new DebugIdentityNode())
-  val axiTimer = LazyModule(new AXI4Timer(sim = true, addressSet))
+  val axiTimer = LazyModule(new AXI4Timer(sim = true, Seq(addressSet)))
 
   axiTimer.node :=
     AXI4UserYanker() :=

src/test/scala/top/SimMMIO.scala

@@ -9,14 +9,14 @@ import freechips.rocketchip.tilelink.{TLErrorEvaluator, TLMasterParameters, TLXb
 
 class SimMMIO()(implicit p: config.Parameters) extends LazyModule {
 
-  val uart = LazyModule(new AXI4UART(AddressSet(0x40600000L, 0xf)))
+  val uart = LazyModule(new AXI4UART(Seq(AddressSet(0x40600000L, 0xf))))
   val vga = LazyModule(new AXI4VGA(
     sim = false,
-    fbAddress = AddressSet(0x50000000L, 0x3fffffL),
-    ctrlAddress = AddressSet(0x40001000L, 0x7L)
+    fbAddress = Seq(AddressSet(0x50000000L, 0x3fffffL)),
+    ctrlAddress = Seq(AddressSet(0x40001000L, 0x7L))
   ))
-  val flash = LazyModule(new AXI4Flash(AddressSet(0x40000000L, 0xfff)))
-  val sd = LazyModule(new AXI4DummySD(AddressSet(0x40002000L, 0xfff)))
+  val flash = LazyModule(new AXI4Flash(Seq(AddressSet(0x40000000L, 0xfff))))
+  val sd = LazyModule(new AXI4DummySD(Seq(AddressSet(0x40002000L, 0xfff))))
 
   val axiBus = AXI4Xbar()
 

src/test/scala/top/XSSim.scala

@@ -70,7 +70,7 @@ class XSSimTop()(implicit p: config.Parameters) extends LazyModule {
 
   val soc = LazyModule(new XSSoc())
   val axiRam = LazyModule(new AXI4RAM(
-    memAddressSet,
+    Seq(memAddressSet),
     memByte = 128 * 1024 * 1024,
     useBlackBox = true
   ))