just send data to lsroq to shorten load miss penalty.

Now DCache has several configurable parameters:
1. nSets
2. nWays
3. blockByte(size block in bytes)
4. rowBits(basic storage unit of cache, the width of a signal sram bank)
5. wordBits(inner cpu bus width) = DataBits = XLEN = 64
6. beatBits(outer tilelink bus width) = l1BusDataWidth = 256

Now, we require beatBits >= rowBits >= wordBits.

Only assert not correctable when we hit and has valid data.

Also, we use ErrGen to help testing our implementation.

We do not block it, we nack it and let it go.

request.

when pipeline stage holds no valid req.

* DCacheLoadReq -> DCacheWordReq
* DCacheStoreReq -> DCacheLineReq

We will use them for synchronization later.
Also, we add get_idx/tag/block_addr/beat stuff.
So next time, use these functions instead of manually manipulating bits.