DCache: make ldu non-blocking.

We do not block it, we nack it and let it go.

src/main/scala/xiangshan/cache/dcacheWrapper.scala

@@ -218,9 +218,10 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
   loadArb.io.in(1) <> lsu_0.req
   assert(!(lsu_0.req.fire() && lsu_0.req.bits.meta.replay), "LSU should not replay requests")
   assert(!(loadReplay.req.fire() && !loadReplay.req.bits.meta.replay), "LoadMissQueue should replay requests")
-  val ldu_0_block = block_load(loadArb.io.out.bits.addr)
-  // do not block replayed reqs
-  block_decoupled(loadArb.io.out, ldu_0.req, ldu_0_block && !loadArb.io.out.bits.meta.replay)
+  val ldu_0_nack = nack_load(loadArb.io.out.bits.addr)
+  // do not nack replayed reqs
+  ldu_0.req <> loadArb.io.out
+  ldu(0).io.nack := ldu_0_nack && !loadArb.io.out.bits.meta.replay
 
   ldu_0.resp.ready := false.B
 
@@ -242,8 +243,10 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
   ldu_0.s1_kill := lsu_0.s1_kill
 
   for (w <- 1 until LoadPipelineWidth) {
-    val load_w_block = block_load(io.lsu.load(w).req.bits.addr)
-    block_decoupled(io.lsu.load(w).req, ldu(w).io.lsu.req, load_w_block)
+    val load_w_nack = nack_load(io.lsu.load(w).req.bits.addr)
+    ldu(w).io.lsu.req <> io.lsu.load(w).req
+    ldu(w).io.nack := load_w_nack
+
     ldu(w).io.lsu.resp <> io.lsu.load(w).resp
     ldu(w).io.lsu.s1_kill <> io.lsu.load(w).s1_kill
     assert(!(io.lsu.load(w).req.fire() && io.lsu.load(w).req.bits.meta.replay), "LSU should not replay requests")
@@ -464,7 +467,7 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
   TLArbiter.lowestFromSeq(edge, bus.c, Seq(prober.io.rep, wb.io.release))
 
   // synchronization stuff
-  def block_load(addr: UInt) = {
+  def nack_load(addr: UInt) = {
     val store_addr_matches = VecInit(stu.io.inflight_req_block_addrs map (entry => entry.valid && entry.bits === get_block_addr(addr)))
     val store_addr_match = store_addr_matches.reduce(_||_)
 

src/main/scala/xiangshan/cache/ldu.scala

@@ -13,12 +13,23 @@ class LoadPipe extends DCacheModule
     val data_resp = Input(Vec(nWays, Vec(refillCycles, Bits(encRowBits.W))))
     val meta_read = DecoupledIO(new L1MetaReadReq)
     val meta_resp = Input(Vec(nWays, new L1Metadata))
+
+    // req got nacked in stage 0?
+    val nack      = Input(Bool())
   })
 
   // LSU requests
-  io.lsu.req.ready := io.meta_read.ready && io.data_read.ready
-  io.meta_read.valid := io.lsu.req.valid
-  io.data_read.valid := io.lsu.req.valid
+  // replayed req should never be nacked
+  assert(!(io.lsu.req.valid && io.lsu.req.bits.meta.replay && io.nack))
+
+  // it you got nacked, you can directly passdown
+  val not_nacked_ready = io.meta_read.ready && io.data_read.ready
+  val nacked_ready     = true.B
+
+  // ready can wait for valid
+  io.lsu.req.ready := io.lsu.req.valid && ((!io.nack && not_nacked_ready) || (io.nack && nacked_ready))
+  io.meta_read.valid := io.lsu.req.valid && !io.nack
+  io.data_read.valid := io.lsu.req.valid && !io.nack
 
   val meta_read = io.meta_read.bits
   val data_read = io.data_read.bits
@@ -46,7 +57,7 @@ class LoadPipe extends DCacheModule
   val s1_req = RegNext(s0_req)
   val s1_valid = RegNext(s0_valid, init = false.B)
   val s1_addr = s1_req.addr
-  val s1_nack = false.B 
+  val s1_nack = RegNext(io.nack)
 
   dump_pipeline_reqs("LoadPipe s1", s1_valid, s1_req)
 

src/main/scala/xiangshan/mem/LoadUnit.scala

@@ -162,7 +162,9 @@ class LoadUnit extends XSModule {
     l4_out.bits.mask  := io.dcache.resp.bits.meta.mask
     // when we can get the data completely from forward
     // we no longer need to access dcache
-    l4_out.bits.miss  := Mux(fullForward, false.B, io.dcache.resp.bits.miss)
+    // treat nack as miss
+    l4_out.bits.miss  := Mux(fullForward, false.B,
+      io.dcache.resp.bits.miss || io.dcache.resp.bits.nack)
     XSDebug(io.dcache.resp.fire(), p"DcacheResp(l4): data:0x${Hexadecimal(io.dcache.resp.bits.data)} paddr:0x${Hexadecimal(io.dcache.resp.bits.meta.paddr)} pc:0x${Hexadecimal(io.dcache.resp.bits.meta.uop.cf.pc)} roqIdx:${io.dcache.resp.bits.meta.uop.roqIdx} lsroqIdx:${io.dcache.resp.bits.meta.uop.lsroqIdx} miss:${io.dcache.resp.bits.miss}\n")
   } .otherwise {
     l4_out.bits := l4_bundle