- 20 12月, 2021 1 次提交
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由 Li Qianruo 提交于
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- 16 12月, 2021 1 次提交
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由 Li Qianruo 提交于
We have singlestep already so triggers do not need to hit after inst commits
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- 10 12月, 2021 3 次提交
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由 Li Qianruo 提交于
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由 William Wang 提交于
* mem,cacheop: fix read data writeback * mem,cacheop: rename cacheop state bits These bits are different from w_*, s_* bits in cache * mem: enable icache op feedback * icache: update cache op implementation * chore: remove cache op logic from XSCore.scala
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由 Yinan Xu 提交于
This commit optimizes the coding style and timing for hardware performance counters. By default, performance counters are RegNext(RegNext(_)).
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- 09 12月, 2021 2 次提交
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由 Jay 提交于
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由 Yinan Xu 提交于
This commit adds WritebackSink and WritebackSource parameters for multiple modules. These traits hide implementation details from other modules by defining IO-related functions in modules. By using WritebackSink, ROB is able to choose the writeback sources. Now fflags and exceptions are connected from exe units to reduce write ports and optimize timing. Further optimizations on write-back to RS and better coding style to be added later.
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- 08 12月, 2021 1 次提交
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由 rvcoresjw 提交于
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- 07 12月, 2021 1 次提交
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由 Jay 提交于
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- 06 12月, 2021 4 次提交
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由 Jay 提交于
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由 Jay 提交于
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由 Jiawei Lin 提交于
* SoC: add axi4spliter * pmp: add apply method to reduce loc * pma: add PMA used in axi4's spliter * Fix package import * pma: re-write tl-pma, put tl-pma into AXI4Spliter * pma: add memory mapped pma * soc: rm dma port, rm axi4spliter, mv mmpma out of spliter * Remove unused files * update dma pma check port at SimTop.scala; update pll lock defalt value to 1 Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn> Co-authored-by: Nrvcoresjw <shangjiawei@rvcore.com>
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由 Jay 提交于
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- 05 12月, 2021 1 次提交
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由 Jay 提交于
* use toMeta.fire() will cause data miss match when toMeta.valid := req.valid
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- 04 12月, 2021 1 次提交
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由 Jay 提交于
* ICache: add ReplacePipe for Probe & Release * remove ProbeUnit * Probe & Release enter ReplacePipe * fix bugs when running Linux on MinimalConfig * TODO: set conflict for ReplacePipe * ICache: add Block logic for ReplacePipe * ReplacePipe: change probe assert condition * support Probe NToN (Probe not hit in ICache) * ICache: fix a bug in meta_write_arb
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- 01 12月, 2021 1 次提交
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由 Jay 提交于
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- 28 11月, 2021 1 次提交
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由 Jay 提交于
* ICache: metaArray & dataArray use bank interleave * ICache: add bank interleave * ICache: add parity check for meta and data arrays * IFU: fix bug in secondary miss * secondary miss doesn't send miss request to miss queue * ICache: write back cancled miss request * ICacheMissEntry: add second miss merge * deal with situations that this entry has been flushed, and the next miss req just requests the same cachline. * ICache: add acquireBlock and GrantAck support * refact: move icache modules to frontend modules * ICache: add release surport and meta coh * ICache: change Get to AcquireBlock for A channel * rebuild: change ICachePara package for other file * ICache: add tilelogger for L1I * ICahce: add ProbeQueue and Probe Process Unit * ICache: add support for ProbeData * ICahceParameter: change tag code to ECC * ICahce: fix bugs in connect and ProbeUnit * metaArray/dataArray responses are not connected * ProbeUnit use reg so data and req are not synchronized * RealeaseUnit: write back mata when voluntary * Add ICache CacheInstruction * move ICache to xiangshan.frontend.icache._ * ICache: add CacheOpDecoder * change ICacheMissQueue to ICacheMissUnit * ProbeUnit: fix meta data not latch bug * IFU: delete releaseSlot and add missSlot * IFU: fix bugs in missSlot state machine * IFU: fix some bugs in miss Slot * IFU: move out fetch to ICache Array logic * ReleaseUnit: delete release write logic * MissUnit: send Release to ReleaseUnit after GAck * ICacheMainPipe: add mainpipe and stop logic * when f3_ready is low, stop the pipeline * IFU: move tlb and array access to mainpipe * Modify Frontend and ICache top for mainpipe * ReleaseUnit: add probe merge status register * ICache: add victim info and release in mainpipe * ICahche: add set-conflict logic * Release: do not invalid meta after sending release * bump Huancun: fix probe problem * bump huancun for MinimalConfig combinational loop * ICache: add LICENSE for new files * Chore: remove debug code and add perf counter * Bump huancun for bug fix * Bump HuanCun for alias bug * ICache: add dirty state for CliendMeta
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- 26 11月, 2021 2 次提交
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由 Lingrui98 提交于
* use one hot muxes for ftb read resp * generate branch history shift one hot vec for history update src sel and update for all possible shift values
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由 Lingrui98 提交于
* decouple fall through address calculating logic from the pftAddr interface * let ghr update from s1 has the highest priority * fix the physical priority of PhyPriorityMuxGenerator
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- 25 11月, 2021 1 次提交
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由 Lingrui98 提交于
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- 23 11月, 2021 1 次提交
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由 William Wang 提交于
* mdp: implement SSIT with sram * mdp: use robIdx instead of sqIdx Dispatch refactor moves lsq enq to dispatch2, as a result, mdp can not get correct sqIdx in dispatch. Unlike robIdx, it is hard to maintain a "speculatively assigned" sqIdx, as it is hard to track store insts in dispatch queue. Yet we can still use "speculatively assigned" robIdx for memory dependency predictor. For now, memory dependency predictor uses "speculatively assigned" robIdx to track inflight store. However, sqIdx is still used to track those store which's addr is valid but data it not valid. When load insts try to get forward data from those store, load insts will get that store's sqIdx and wait in RS. They will not waken until store data with that sqIdx is issued. * mdp: add track robIdx recover logic
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- 18 11月, 2021 3 次提交
- 16 11月, 2021 2 次提交
- 15 11月, 2021 2 次提交
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由 zoujr 提交于
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由 Li Qianruo 提交于
* Untested Trigger Implementation Co-authored-by: NWilliam Wang <zeweiwang@outlook.com> Co-authored-by: NLingrui98 <goulingrui19s@ict.ac.cn> Co-authored-by: Nrvcoresjw <shangjiawei@rvcore.com>
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- 14 11月, 2021 2 次提交
- 13 11月, 2021 2 次提交
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由 Lingrui98 提交于
* fix a bug of wrongly discarding some new bits to be xored * ghr should be longer in default config to avoid falsely overriding * move TageBanks to top, and fix SC folded history config
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由 Lingrui98 提交于
* fix a bug of wrongly discarding some new bits to be xored * ghr should be longer in default config to avoid falsely overriding * move TageBanks to top, and fix SC folded history config
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- 12 11月, 2021 4 次提交
- 11 11月, 2021 1 次提交
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由 Lingrui98 提交于
* use compressed info to do redirects * implement folded history class
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- 09 11月, 2021 2 次提交
- 05 11月, 2021 1 次提交
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由 Jay 提交于
* IFU: move mmio to f3 and wait commit * IFU: fix mmio_has_commit condition * compare FtqPtr to ensure the mmio instruction has been committed * Uncache fetch : cancel flush when backend redirect
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