- 20 12月, 2021 1 次提交
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由 Li Qianruo 提交于
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- 16 12月, 2021 1 次提交
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由 Li Qianruo 提交于
We have singlestep already so triggers do not need to hit after inst commits
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- 13 12月, 2021 3 次提交
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由 Li Qianruo 提交于
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由 Li Qianruo 提交于
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由 William Wang 提交于
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- 12 12月, 2021 3 次提交
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由 Li Qianruo 提交于
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由 Li Qianruo 提交于
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由 William Wang 提交于
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- 10 12月, 2021 6 次提交
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由 Li Qianruo 提交于
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由 Li Qianruo 提交于
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由 William Wang 提交于
* mem,cacheop: fix read data writeback * mem,cacheop: rename cacheop state bits These bits are different from w_*, s_* bits in cache * mem: enable icache op feedback * icache: update cache op implementation * chore: remove cache op logic from XSCore.scala
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由 William Wang 提交于
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由 Yinan Xu 提交于
This commit optimizes the coding style and timing for hardware performance counters. By default, performance counters are RegNext(RegNext(_)).
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由 wakafa 提交于
* bump huancun * bump huancun * Bump huancun Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>
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- 09 12月, 2021 5 次提交
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由 Jay 提交于
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由 Yinan Xu 提交于
This commit adds WritebackSink and WritebackSource parameters for multiple modules. These traits hide implementation details from other modules by defining IO-related functions in modules. By using WritebackSink, ROB is able to choose the writeback sources. Now fflags and exceptions are connected from exe units to reduce write ports and optimize timing. Further optimizations on write-back to RS and better coding style to be added later.
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由 Li Qianruo 提交于
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由 Li Qianruo 提交于
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由 Li Qianruo 提交于
The bugs are 1. Debug mode ebreak won't cause exception 2. faulty mcontrol load store execute bits
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- 08 12月, 2021 5 次提交
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由 Lemover 提交于
* csr.satp: add r/w mask of ppn part * ci: add unit test, satp should concern PADDRBITS * csr.xstatus: XS field is ready-only * bump ready-to-run * bump ready-to-run, update nemu so * fix typo
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由 William Wang 提交于
Now we RegNext(refill_req) for 1 cycle. It will provide more time for refillShouldBeBlocked calcuation
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由 William Wang 提交于
* dcache: give probe the highest priority * dcache: fix block probe logic * dcache: give replace_req higher priority
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由 rvcoresjw 提交于
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由 Li Qianruo 提交于
The bugs are 1. Debug mode ebreak won't cause exception 2. faulty mcontrol load store execute bits
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- 07 12月, 2021 3 次提交
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由 William Wang 提交于
* mem,cacheop: fix read data writeback * mem,cacheop: rename cacheop state bits These bits are different from w_*, s_* bits in cache
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由 Jay 提交于
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由 Jiawei Lin 提交于
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- 06 12月, 2021 9 次提交
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由 Jay 提交于
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由 Jay 提交于
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由 Li Qianruo 提交于
This bug occurs when rem is 0 and dividend is negative Caused by a buggy rightshifter
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由 Jiawei Lin 提交于
* SoC: add axi4spliter * pmp: add apply method to reduce loc * pma: add PMA used in axi4's spliter * Fix package import * pma: re-write tl-pma, put tl-pma into AXI4Spliter * pma: add memory mapped pma * soc: rm dma port, rm axi4spliter, mv mmpma out of spliter * Remove unused files * update dma pma check port at SimTop.scala; update pll lock defalt value to 1 Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn> Co-authored-by: Nrvcoresjw <shangjiawei@rvcore.com>
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由 William Wang 提交于
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由 Jay 提交于
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由 Lemover 提交于
* csr: clear mstatus.mprv when mstatus.mpp != ModeM at xret * csr: add mconfigptr, but hardwire to 0 now * csr: add *BE to mstatusStruct which are hardwired to 0 * csr: fix bug of xret clear mprv * ci: add unit test, xret clear mstatus.mprv when xpp is not M * bump ready-to-run
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由 Yinan Xu 提交于
This commit changes the splitN algorithm for the write-back arbiter. Previously we split the function units as follows: (FU0 FU1 FU2) (FU3 FU4 FU5). However, this strategy tends to group the function units with the same type into the same arbiter and may cause performance loss. In this commit, we change the strategy to: (FU0 FU2 FU4) (FU1 FU3 FU5).
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由 Yinan Xu 提交于
This commit optimizes the issue grant timing when age is enabled. Select from age and SelectPolicy are processed parallely.
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- 05 12月, 2021 4 次提交
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由 wakafa 提交于
* bump huancun
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由 William Wang 提交于
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由 Yinan Xu 提交于
This commit adds an interrupt_safe flag that tracks whether an instruction is safe for interrupts. For example, any MMIO instruction is not safe because it changes the external devices before write-back.
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由 Yinan Xu 提交于
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