ICacheMainPipe: fix a bug in set conflict (#1284)

src/main/scala/xiangshan/frontend/icache/ICache.scala

@@ -556,7 +556,7 @@ class ICacheImp(outer: ICache) extends LazyModuleImp(outer) with HasICacheParame
   val fetchShouldBlock = VecInit(fetchReq.map(req => VecInit(hasMiss.zip(missSetSeq).map{case(valid, idx)=>  valid && idx === req.bits.vsetIdx}).reduce(_||_)))
   
   (0 until PortNumber).map{i => 
-      mainpipe.io.fetch(i).req.valid := io.fetch(i).req.valid && !fetchShouldBlock(i)
+      mainpipe.io.fetch(i).req.valid := io.fetch(i).req.valid //&& !fetchShouldBlock(i)
       io.fetch(i).req.ready          :=  mainpipe.io.fetch(i).req.ready && !fetchShouldBlock(i)
       mainpipe.io.fetch(i).req.bits  := io.fetch(i).req.bits
   }

src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala

@@ -139,7 +139,7 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule
   //fetch: send addr to Meta/TLB and Data simultaneously
   val fetch_req = List(toMeta, toData)
   for(i <- 0 until 2) {
-    fetch_req(i).valid             := s0_fire
+    fetch_req(i).valid             := s0_valid
     fetch_req(i).bits.isDoubleLine := s0_double_line
     fetch_req(i).bits.vSetIdx      := s0_req_vsetIdx
   }
@@ -550,7 +550,7 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule
 
   (0 until PortNumber).map{ i =>
     io.setInfor.s2(i).valid := s2_bank_miss(i) && s2_valid
-    io.setInfor.s2(i).vidx  := s1_req_vsetIdx(i)
+    io.setInfor.s2(i).vidx  := s2_req_vsetIdx(i)
   }
 
   val miss_all_fix       =  wait_state === wait_finish