* when TLB req has been latched into tlb_slot, the
tlb_all_resp condition, which affects s0_fire should
depend on the slot result.

branch prediction optimizations and bug fixes

add one cycle on ifu/backend redirect

Rocket's Debug Module uses unaligned Get and Put to access physical memory. However, our non-inclusive L3 does not have very good support for non-aligned Puts and Gets, so here 256-bit aligned PutPartial and Get is used.
Currently on every request, only 1 byte of data is stored using mask, and only one byte of loaded data is used, because otherwise it would require a lot more modification to Rocket's code.
Note that this feature is currently only usable with DefaultConfig.

* dcache: fix bug that a block could be released twice

* MainPipe: fix bug in way_en of miss_req

* MainPipe: fix bug

bump bpu timing

This commit fixes the block_commit condition when an instruction has
exception but labeled flushPipe. Previously such an instruction will
commit normally.