- 02 9月, 2021 1 次提交
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由 Lemover 提交于
* Revert "Revert "l0tlb: add a new level tlb to each mem pipeline (#936)" (#945)" This reverts commit b052b972. * fu: remove unused import * mmu.tlb: 2 load/store pipeline has 1 dtlb * mmu: remove btlb, the l1-tlb * mmu: set split-tlb to 32 to check perf effect * mmu: wrap tlb's param with TLBParameters * mmu: add params 'useBTlb' dtlb size is small: normal 8, super 2 * mmu.tlb: add Bundle TlbEntry, simplify tlb hit logic(coding) * mmu.tlb: seperate tlb's storage, relative hit/sfence logic tlb now supports full-associate, set-associate, directive-associate. more: change tlb's parameter usage, change util.Random to support case that mod is 1. * mmu.tlb: support normalAsVictim, super(fa) -> normal(sa/da) be carefull to use tlb's parameter, only a part of param combination is supported * mmu.tlb: fix bug of hit method and victim write * mmu.tlb: add tlb storage's perf counter * mmu.tlb: rewrite replace part, support set or non-set * mmu.tlb: add param outReplace to receive out replace index * mmu.tlb: change param superSize to superNWays add param superNSets, which should always be 1 * mmu.tlb: change some perf counter's name and change some params * mmu.tlb: fix bug of replace io bundle * mmu.tlb: remove unused signal wayIdx in tlbstorageio * mmu.tlb: separate tlb_ld/st into two 'same' tlb * mmu.tlb: when nWays is 1, replace returns 0.U before, replace will return 1.U, no influence for refill but bad for perf counter * mmu.tlb: give tlb_ld and tlb_st a name (in waveform)
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- 23 8月, 2021 1 次提交
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- 22 8月, 2021 1 次提交
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由 Lemover 提交于
* Miniconfig: change dtlb size to 32 at minimal config * mmu.dtlb: change tlb's replacement access code style dtlb now can support plru (functionaly). plru with multi-access is chained, so there will be long latency for dtlb to use plru. * mmu.tlb: add tlb at new level named btlb bridge tlb: one l0-tlb in each mem pipeline all the l0-tlb connect to bridge tlb btlb connects to l2tlb, so btlb is also l1-tlb itlb remains the same * mmu.tlb: set tlb size: l0-8, l1-64 * mmu.btlb: add sfence logic * mmu.tlb: fix bug of sfence logic of g bit * mmu.btlb: add some perf counter * mmu.btlb: fix bug of random replace * mmu.filter: add port vector to record which ports the reqs come from * mmu.btlb: add some perf counter && add refill mask * mmu.filter: add check for flushed req
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- 24 7月, 2021 1 次提交
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由 Yinan Xu 提交于
XiangShan is jointly released by ICT and PCL.
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- 19 7月, 2021 1 次提交
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由 Lemover 提交于
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- 04 6月, 2021 1 次提交
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由 Lemover 提交于
In this commit, we add License for XiangShan project.
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- 09 5月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit replaces src1, src2, src3 in Bundle ExuInput with Vec(3, UInt). Should be easier for RS.
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- 30 4月, 2021 1 次提交
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由 William Wang 提交于
* RSFeedback: add source type * StoreQueue: split store addr and store data * StoreQueue: update ls forward logic * Now it supports splited addr and data * Chore: force assign name for load/store unit * RS: add rs'support for store a-d split * StoreQueue: fix stlf logic * StoreQueue: fix addr wb sq update logic * AtomicsUnit: support splited a/d * StoreQueue: add sbuffer enq condition assertion Store data op (std) may still be invalid after store addr op's (sta) commitment, so datavalid needs to be checked before commiting store data to sbuffer Note that at current commit a non-completed std op for a commited store may exist. We should make sure that uop will not be cancelled by a latter branch mispredict. More work to be done! * Roq: add std/sta split writeback logic Now store will commit only if both sta & std have been writebacked Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
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- 28 4月, 2021 1 次提交
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由 Lemover 提交于
* Perf: add perf counter for addr gen, across page or not * Perf: add perf counter for addr gen, just record first issue
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- 19 4月, 2021 1 次提交
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由 Jiawei Lin 提交于
* difftest: use DPI-C to refactor difftest In this commit, difftest is refactored with DPI-C calls. There're a few reasons: (1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr. (2) DPI-C is cross-platform (Verilator, VCS, ...) (3) difftest APIs are splited from emu.cpp to possibly support more backend platforms (NEMU, Spike, ...) The performance at this commit is quite slower than the original emu. Performance issues will be fixed later. * [WIP] SimTop: try to use 'XSTop' as soc * CircularQueuePtr: ues F-bounded polymorphis instead implict helper * Refactor parameters & Clean up code * difftest: support basic difftest * Support diffetst in new sim top * Difftest; convert recode fmt to ieee754 when comparing fp regs * Difftest: pass sign-ext pc to dpic functions && fix exception pc * Debug: add int/exc inst wb to debug queue * Difftest: pass sign-ext pc to dpic functions && fix exception pc * Difftest: fix naive commit num limit Co-authored-by: NYinan Xu <xuyinan1997@gmail.com> Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
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- 13 3月, 2021 1 次提交
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由 Lemover 提交于
just record the tlb result(access and miss) of first issue by add signal isFirstIssue (isFirstIssue = cntCountQueue(i) === 0.U)
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- 05 3月, 2021 1 次提交
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由 Lemover 提交于
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- 19 2月, 2021 1 次提交
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由 William Wang 提交于
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- 03 2月, 2021 1 次提交
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由 William Wang 提交于
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- 31 1月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 30 1月, 2021 1 次提交
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由 ZhangZifei 提交于
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- 29 1月, 2021 1 次提交
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由 William Wang 提交于
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- 27 1月, 2021 1 次提交
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由 wangkaifan 提交于
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- 26 1月, 2021 1 次提交
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由 William Wang 提交于
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- 25 1月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 22 1月, 2021 2 次提交
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由 Lingrui98 提交于
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由 William Wang 提交于
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- 16 1月, 2021 2 次提交
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由 William Wang 提交于
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由 William Wang 提交于
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- 15 1月, 2021 1 次提交
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由 William Wang 提交于
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- 14 1月, 2021 3 次提交
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由 Yinan Xu 提交于
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由 wangkaifan 提交于
* values of hardware performance counters can hardly be emulated by NEMU
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由 LinJiawei 提交于
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- 07 1月, 2021 1 次提交
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由 William Wang 提交于
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- 06 1月, 2021 1 次提交
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由 William Wang 提交于
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- 16 12月, 2020 1 次提交
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由 Yinan Xu 提交于
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- 15 12月, 2020 2 次提交
- 14 12月, 2020 1 次提交
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由 Yinan Xu 提交于
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- 13 12月, 2020 2 次提交
- 11 12月, 2020 1 次提交
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由 Yinan Xu 提交于
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- 30 11月, 2020 1 次提交
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由 William Wang 提交于
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- 28 11月, 2020 2 次提交
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由 William Wang 提交于
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由 William Wang 提交于
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