store unit: send s1_paddr to lsq in stage 1

src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala

@@ -78,6 +78,7 @@ class StoreUnit_S1 extends XSModule {
   // writeback store inst to lsq
   io.lsq.valid := io.in.valid // TODO: && ! FP
   io.lsq.bits := io.in.bits
+  io.lsq.bits.paddr := s1_paddr
   io.lsq.bits.miss := false.B
   io.lsq.bits.mmio := AddressSpace.isMMIO(s1_paddr)