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    l0tlb: add a new level tlb to each mem pipeline (#936) · 5aae5b8d
    Lemover 提交于
    * Miniconfig: change dtlb size to 32 at minimal config
    
    * mmu.dtlb: change tlb's replacement access code style
    
    dtlb now can support plru (functionaly).
    plru with multi-access is chained, so there will be long latency
      for dtlb to use plru.
    
    * mmu.tlb: add tlb at new level named btlb
    
    bridge tlb:
    one l0-tlb in each mem pipeline
    all the l0-tlb connect to bridge tlb
    btlb connects to l2tlb, so btlb is also l1-tlb
    itlb remains the same
    
    * mmu.tlb: set tlb size: l0-8, l1-64
    
    * mmu.btlb: add sfence logic
    
    * mmu.tlb: fix bug of sfence logic of g bit
    
    * mmu.btlb: add some perf counter
    
    * mmu.btlb: fix bug of random replace
    
    * mmu.filter: add port vector to record which ports the reqs come from
    
    * mmu.btlb: add some perf counter && add refill mask
    
    * mmu.filter: add check for flushed req
    5aae5b8d
StoreUnit.scala 8.2 KB