load,store: don't mark the instruction as mmio if it has exceptions

src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala

@@ -237,7 +237,7 @@ class LoadQueue extends XSModule
   })).asUInt() // use uint instead vec to reduce verilog lines
   val evenDeqMask = getEvenBits(deqMask)
   val oddDeqMask = getOddBits(deqMask)
-  // generate lastCycleSelect mask 
+  // generate lastCycleSelect mask
   val evenSelectMask = Mux(io.ldout(0).fire(), getEvenBits(UIntToOH(loadWbSel(0))), 0.U)
   val oddSelectMask = Mux(io.ldout(1).fire(), getOddBits(UIntToOH(loadWbSel(1))), 0.U)
   // generate real select vec
@@ -254,7 +254,7 @@ class LoadQueue extends XSModule
   loadWbSelVGen(0):= loadEvenSelVec.asUInt.orR
   loadWbSelGen(1) := Cat(getFirstOne(toVec(loadOddSelVec), oddDeqMask), 1.U(1.W))
   loadWbSelVGen(1) := loadOddSelVec.asUInt.orR
-  
+
   (0 until LoadPipelineWidth).map(i => {
     loadWbSel(i) := RegNext(loadWbSelGen(i))
     loadWbSelV(i) := RegNext(loadWbSelVGen(i), init = false.B)
@@ -462,7 +462,7 @@ class LoadQueue extends XSModule
   val lastCycleRedirect = RegNext(io.brqRedirect)
   val lastCycleFlush = RegNext(io.flush)
 
-  // S2: select rollback and generate rollback request 
+  // S2: select rollback and generate rollback request
   // Note that we use roqIdx - 1.U to flush the load instruction itself.
   // Thus, here if last cycle's roqIdx equals to this cycle's roqIdx, it still triggers the redirect.
   val rollbackGen = Wire(Valid(new Redirect))
@@ -483,7 +483,7 @@ class LoadQueue extends XSModule
 
   // S3: fire rollback request
   io.rollback := rollbackReg
-  io.rollback.valid := rollbackReg.valid && 
+  io.rollback.valid := rollbackReg.valid &&
     (!lastCycleRedirect.valid || !isAfter(rollbackReg.bits.roqIdx, lastCycleRedirect.bits.roqIdx)) &&
     !lastCycleFlush
 

src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala

@@ -30,7 +30,7 @@ class LoadUnit_S0 extends XSModule {
   val s0_vaddr_old = io.in.bits.src1 + SignExt(ImmUnion.I.toImm32(s0_uop.ctrl.imm), XLEN)
   val imm12 = WireInit(s0_uop.ctrl.imm(11,0))
   val s0_vaddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12)
-  val s0_vaddr_hi = Mux(imm12(11), 
+  val s0_vaddr_hi = Mux(imm12(11),
     Mux((s0_vaddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12)),
     Mux((s0_vaddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12)+1.U, io.in.bits.src1(VAddrBits-1, 12))
   )
@@ -152,8 +152,8 @@ class LoadUnit_S2 extends XSModule with HasLoadHelper {
   val s2_mask = io.in.bits.mask
   val s2_paddr = io.in.bits.paddr
   val s2_tlb_miss = io.in.bits.tlbMiss
-  val s2_mmio = io.in.bits.mmio
   val s2_exception = selectLoad(io.in.bits.uop.cf.exceptionVec, false).asUInt.orR
+  val s2_mmio = io.in.bits.mmio && !s2_exception
   val s2_cache_miss = io.dcacheResp.bits.miss
   val s2_cache_replay = io.dcacheResp.bits.replay
 

src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala

@@ -20,7 +20,7 @@ class StoreUnit_S0 extends XSModule {
   val saddr_old = io.in.bits.src1 + SignExt(ImmUnion.S.toImm32(io.in.bits.uop.ctrl.imm), XLEN)
   val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0))
   val saddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12)
-  val saddr_hi = Mux(imm12(11), 
+  val saddr_hi = Mux(imm12(11),
     Mux((saddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12)),
     Mux((saddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12)+1.U, io.in.bits.src1(VAddrBits-1, 12))
   )
@@ -73,6 +73,8 @@ class StoreUnit_S1 extends XSModule {
 
   val s1_paddr = io.dtlbResp.bits.paddr
   val s1_tlb_miss = io.dtlbResp.bits.miss
+  val s1_mmio = io.dtlbResp.bits.mmio
+  val s1_exception = selectStore(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR
 
   io.in.ready := true.B
 
@@ -95,13 +97,12 @@ class StoreUnit_S1 extends XSModule {
   io.lsq.bits := io.in.bits
   io.lsq.bits.paddr := s1_paddr
   io.lsq.bits.miss := false.B
-  io.lsq.bits.mmio := io.dtlbResp.bits.mmio
+  io.lsq.bits.mmio := s1_mmio && !s1_exception
   io.lsq.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st
   io.lsq.bits.uop.cf.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp.af.st
 
   // mmio inst with exception will be writebacked immediately
-  val hasException = selectStore(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR
-  io.out.valid := io.in.valid && (!io.out.bits.mmio || hasException) && !s1_tlb_miss
+  io.out.valid := io.in.valid && (!io.out.bits.mmio || s1_exception) && !s1_tlb_miss
   io.out.bits := io.lsq.bits
 
   // encode data for fp store