- 10 11月, 2022 1 次提交
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由 Jenius 提交于
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- 09 11月, 2022 39 次提交
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由 Jenius 提交于
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由 Jenius 提交于
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由 Jenius 提交于
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由 Jenius 提交于
* add 1 stage for mmio_state before sending request to MMIO bus * check whether the last fetch packet commit all its intructions (the result of execution path has been decided) * avoid speculative execution to MMIO bus
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Jenius 提交于
* when f3_flush is enabled, f3_lastHalf_disable is still set and influence the next packet
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由 Jenius 提交于
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由 Guokai Chen 提交于
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由 Jenius 提交于
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由 Jenius 提交于
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由 Lingrui98 提交于
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由 Jenius 提交于
* Under the circumstance that 2 continuous ftq reqs both have last half RVI, but the f3_lastHalf.valid cancel condition in wb-stage is set by !f3_lastHalf.valid, which makes the miss pred f3_lastHalf req has not been flushed.
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Jenius 提交于
* reset state_vec register in replacement
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由 Jenius 提交于
* latch arbiter out before entering dataArray, without which will causes write valid ( state_reg ) fanout to every bit of WEM and D of SRAM
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由 Lingrui98 提交于
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由 Lingrui98 提交于
Previously the BranchPredictionUpdate bundle was inherited from BranchPredictionBundle, and that made some field of the bundle unused. It was hard to find which signals are really in use. Now we make BranchPredictionUpdate a independent bundle, so that the signals in it are all in use.
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由 Jenius 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Jenius 提交于
if a req with a last half but miss predicted enters in wb stage, and this cycle f3 stalls, we set a flag to notify f3 that the last half flag need not to be set.
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Steve Gou 提交于
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由 Yinan Xu 提交于
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由 Jenius 提交于
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由 Jenius 提交于
* <bug-fix> IFU: cancel lastHalf for miss prediction * <bug-fix> ICacheMainPipe: latch tlb resp for stall * <bug-fix> only tlb_slot.valid can raise has_latch
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由 Jenius 提交于
* copy Ftq to ICache read valid signal * move sram read data and miss data selection to IFU (after predecode)
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由 Jenius 提交于
* copy address select signal for every copied port * add 1 more copy for itlb request use * add 1 cycle latency for ftq_pc_mem read before sending to IPrefetch
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由 Jenius 提交于
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由 Jenius 提交于
* this bug is caused by trigger wait_state for a hit pmp af req
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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