* Add ResetRegGen module to generate reset signals for different modules

To meet physical design requirements, reset signals for different modules
need to be generated respectively. This commit adds a ResetRegGen module
to automatically generate reset registers and connects different reset
signals to different modules, including l3cache, l2cache, core.
L1plusCache, MemBlock, IntegerBlock, FloatBlock, CtrlBlock, Frontend are
reset one by one.

* csr: remove unused input perfcnt io

* perfcnt: add some in-core hardware performance counters

* perfcnt: optimize timing for hardware performance counters

* MainPipe/LoadPipe: disable fast wakeup when data sram is to be written

* RS: set EnableLoadFastWakeUp true

* LoadPipe: add perf cnt for disabling ld fast wakeup speculatively

* MainPipe: disable ld fast wakeup when s1 read data in MainPipe
Co-authored-by: Nzhanglinjuan <zhanglinjuan16@mails.ucas.ac.cn>

* LoadUnit: generate fastUop in load_s1

* RS/Load: add load to fast wakeup when cache hit, while maintain its slow

* RS: remove legacy assert that doesn't work for load has fast and slow

* LoadUnit: fix bug that fastUops's valid forgets load_s1.io.in.valid

* MemBlock: fix bug of loadUnit's fast and slow connect

IPC of coremark 10 cycles raise from 1.63 to 1.70

* RS: RegNext srcUpdate to use it at next cycle

* RS: add param EnableLoadFastWakeUp and set default to false
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

* MySoc: verilog top

* MySoc: connect mmio

* MySoc: fix some bugs

* wip

* TopMain: remove to top

* WIP: add dma port

* Update XSTop for FPGA/ASIC platform

* Top: add rocket-chip source

* Append SRAM to generated verilog
Co-authored-by: NLinJiawei <linjiav@outlook.com>

This reverts commit 1c6ad6d0.

* Replacement: fix way method bugs

We do state change when calling way method, but in lack of a signal to
inform whether it is necessary to do state change, this might cause
problem.

* ICache: use new replacement method

* L1plusCache: change replacement method

* L1plusCache: add performance counters.

* L1plusCache: fix performance bug.

ICache miss penalty increases because that we miss the access method
in L1plusCache for replacement :)

* xscore: remove reg and logic in xscore top module

* XSCore: remove logic in top module

* Fp/Int block: fix write back bug
Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>

* core: enable sc

* sc: calculate sum again on update

* sc: clean ups

* sc: add some debug info

* sc, tage, bim: fix wrbypass logic, add wrbypass for SC

* sc: restrict threshold update conditions and prevent overflow problem

* sc: use seperative thresholds for each bank

* sc: update debug info

* sc: use adaptive threshold algorithm from the original O-GEHL

* tage, bim, sc: optimize wrbypass logic

* sc: initialize threshold to 60

* loop: remove unuseful RegNext on redirect

* RS: optimize numExist signal

* RS: fix some typo

* RS: optimize deq logic for block-nonfeedback rs

separate ecc correction from the critical path of dcache resp

* DCache: remove ecc to improve timing.

* MissQueue: refill_arb change RRArbiter to Arbiter to improve timing.

* WaitTable: add waittable framework

* WaitTable: get replay info from RedirectGenerator

* StoreQueue: maintain issuePtr for load rs

* RS: add loadWait to rs (only for load Unit's rs)

* WaitTable: fix update logic

* StoreQueue: fix issuePtr update logic

* chore: set loadWaitBit in ibuffer

* StoreQueue: fix issuePtrExt update logic

Former logic does not work well with mmio logic

We may also make sure that issuePtrExt is not before cmtPtrExt

* WaitTable: write with priority

* StoreQueue: fix issuePtrExt update logic for mmio

* chore: fix typos

* CSR: add slvpredctrl

* slvpredctrl will control load violation predict micro architecture

* WaitTable: use xor folded pc to index waittable
Co-authored-by: NZhangZifei <1773908404@qq.com>

* Backend: fix some bugs related to exu write

* Roq: revert to perv verision

* Fix fp write back bugs