csr: support prefetcher enable control via spfctl CSR

src/main/scala/xiangshan/XSCore.scala

@@ -418,6 +418,7 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
   frontend.io.backend <> ctrlBlock.io.frontend
   frontend.io.sfence <> integerBlock.io.fenceio.sfence
   frontend.io.tlbCsr <> integerBlock.io.csrio.tlb
+  frontend.io.csrCtrl <> integerBlock.io.csrio.customCtrl
 
   frontend.io.icacheMemAcq <> l1pluscache.io.req
   l1pluscache.io.resp <> frontend.io.icacheMemGrant
@@ -463,21 +464,23 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
 	raw
   }))
 
-  integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags
-  integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs
+  integerBlock.io.csrio.perf <> DontCare
+  integerBlock.io.csrio.perf.retiredInstr <> ctrlBlock.io.roqio.toCSR.perfinfo.retiredInstr
+  integerBlock.io.csrio.fpu.fflags <> ctrlBlock.io.roqio.toCSR.fflags
+  integerBlock.io.csrio.fpu.isIllegal := false.B
+  integerBlock.io.csrio.fpu.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs
+  integerBlock.io.csrio.fpu.frm <> floatBlock.io.frm
   integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception
-  integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget
   integerBlock.io.csrio.isXRet <> ctrlBlock.io.roqio.toCSR.isXRet
+  integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget
   integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet
   integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr
   integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt
-  integerBlock.io.csrio.perfinfo <> ctrlBlock.io.roqio.toCSR.perfinfo
+
   integerBlock.io.fenceio.sfence <> memBlock.io.sfence
   integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer
-  memBlock.io.tlbCsr <> integerBlock.io.csrio.tlb
-
-  floatBlock.io.frm <> integerBlock.io.csrio.frm
 
+  memBlock.io.tlbCsr <> integerBlock.io.csrio.tlb
   memBlock.io.lsqio.roq <> ctrlBlock.io.roqio.lsq
   memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.uop.lqIdx
   memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.uop.sqIdx
@@ -504,6 +507,7 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
     l2PrefetcherIn <> memBlock.io.toDCachePrefetch
   }
   l2Prefetcher.io.in <> l2PrefetcherIn
+  l2Prefetcher.io.enable := RegNext(integerBlock.io.csrio.customCtrl.l2_pf_enable)
 
   if (!env.FPGAPlatform) {
     val id = hartIdCore()

src/main/scala/xiangshan/backend/IntegerBlock.scala

@@ -5,7 +5,7 @@ import chisel3.util._
 import xiangshan._
 import xiangshan.backend.exu.Exu.{ldExeUnitCfg, stExeUnitCfg}
 import xiangshan.backend.exu._
-import xiangshan.backend.fu.FenceToSbuffer
+import xiangshan.backend.fu.{FenceToSbuffer, CSRFileIO}
 import xiangshan.backend.issue.{ReservationStation}
 import xiangshan.backend.regfile.Regfile
 
@@ -71,21 +71,7 @@ class IntegerBlock
     val wakeUpFpOut = Flipped(new WakeUpBundle(fastFpOut.size, slowFpOut.size))
     val wakeUpIntOut = Flipped(new WakeUpBundle(fastIntOut.size, slowIntOut.size))
 
-    val csrio = new Bundle {
-      val fflags = Flipped(Valid(UInt(5.W))) // from roq
-      val dirty_fs = Input(Bool()) // from roq
-      val frm = Output(UInt(3.W)) // to float
-      val exception = Flipped(ValidIO(new ExceptionInfo))
-      val trapTarget = Output(UInt(VAddrBits.W)) // to roq
-      val isXRet = Output(Bool())
-      val interrupt = Output(Bool()) // to roq
-      val memExceptionVAddr = Input(UInt(VAddrBits.W)) // from lsq
-      val externalInterrupt = new ExternalInterruptIO  // from outside
-      val tlb = Output(new TlbCsrBundle) // from tlb
-      val perfinfo = new Bundle {
-        val retiredInstr = Input(UInt(3.W))
-      }
-    }
+    val csrio = new CSRFileIO
     val fenceio = new Bundle {
       val sfence = Output(new SfenceBundle) // to front,mem
       val fencei = Output(Bool())           // to icache

src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala

@@ -6,25 +6,11 @@ import chisel3.util._
 import xiangshan._
 import xiangshan.backend.exu.Exu.jumpExeUnitCfg
 import xiangshan.backend.fu.fpu.IntToFP
-import xiangshan.backend.fu.{CSR, Fence, FenceToSbuffer, FunctionUnit, Jump}
+import xiangshan.backend.fu.{CSR, Fence, FenceToSbuffer, FunctionUnit, Jump, CSRFileIO}
 
 class JumpExeUnit extends Exu(jumpExeUnitCfg)
 {
-  val csrio = IO(new Bundle {
-    val fflags = Flipped(ValidIO(UInt(5.W)))
-    val dirty_fs = Input(Bool())
-    val frm = Output(UInt(3.W))
-    val exception = Flipped(ValidIO(new ExceptionInfo))
-    val trapTarget = Output(UInt(VAddrBits.W))
-    val isXRet = Output(Bool())
-    val interrupt = Output(Bool())
-    val memExceptionVAddr = Input(UInt(VAddrBits.W))
-    val externalInterrupt = new ExternalInterruptIO
-    val tlb = Output(new TlbCsrBundle)
-    val perfinfo = new Bundle {
-      val retiredInstr = Input(UInt(3.W))
-    }
-  })
+  val csrio = IO(new CSRFileIO)
   val fenceio = IO(new Bundle {
     val sfence = Output(new SfenceBundle)
     val fencei = Output(Bool())
@@ -69,19 +55,7 @@ class JumpExeUnit extends Exu(jumpExeUnitCfg)
     case i: IntToFP => i
   }.get
 
-  csr.csrio.perf <> DontCare
-  csr.csrio.perf.retiredInstr <> csrio.perfinfo.retiredInstr
-  csr.csrio.fpu.fflags <> csrio.fflags
-  csr.csrio.fpu.isIllegal := false.B
-  csr.csrio.fpu.dirty_fs <> csrio.dirty_fs
-  csr.csrio.fpu.frm <> csrio.frm
-  csr.csrio.exception <> csrio.exception
-  csr.csrio.trapTarget <> csrio.trapTarget
-  csr.csrio.isXRet <> csrio.isXRet
-  csr.csrio.interrupt <> csrio.interrupt
-  csr.csrio.memExceptionVAddr <> csrio.memExceptionVAddr
-  csr.csrio.externalInterrupt <> csrio.externalInterrupt
-  csr.csrio.tlb <> csrio.tlb
+  csr.csrio <> csrio
 
   if (!env.FPGAPlatform) {
     difftestIO.fromCSR <> csr.difftestIO

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -122,27 +122,37 @@ class PerfCounterIO extends XSBundle {
   val value = Input(UInt(XLEN.W))
 }
 
+class CustomCSRCtrlIO extends XSBundle {
+  val l1plus_pf_enable = Output(Bool())
+  val l2_pf_enable = Output(Bool())
+  val dsid = Output(UInt(8.W)) // TODO: DsidWidth as parameter
+}
+
+class CSRFileIO extends XSBundle {
+  // output (for func === CSROpType.jmp)
+  val perf = new PerfCounterIO
+  val isPerfCnt = Output(Bool())
+  // to FPU
+  val fpu = Flipped(new FpuCsrIO)
+  // from rob
+  val exception = Flipped(ValidIO(new ExceptionInfo))
+  // to ROB
+  val isXRet = Output(Bool())
+  val trapTarget = Output(UInt(VAddrBits.W))
+  val interrupt = Output(Bool())
+  // from LSQ
+  val memExceptionVAddr = Input(UInt(VAddrBits.W))
+  // from outside cpu,externalInterrupt
+  val externalInterrupt = new ExternalInterruptIO
+  // TLB
+  val tlb = Output(new TlbCsrBundle)
+  // Prefetcher
+  val customCtrl = Output(new CustomCSRCtrlIO)
+}
+
 class CSR extends FunctionUnit with HasCSRConst
 {
-  val csrio = IO(new Bundle {
-    // output (for func === CSROpType.jmp)
-    val perf = new PerfCounterIO
-    val isPerfCnt = Output(Bool())
-    // to FPU
-    val fpu = Flipped(new FpuCsrIO)
-    // from rob
-    val exception = Flipped(ValidIO(new ExceptionInfo))
-    // to ROB
-    val isXRet = Output(Bool())
-    val trapTarget = Output(UInt(VAddrBits.W))
-    val interrupt = Output(Bool())
-    // from LSQ
-    val memExceptionVAddr = Input(UInt(VAddrBits.W))
-    // from outside cpu,externalInterrupt
-    val externalInterrupt = new ExternalInterruptIO
-    // TLB
-    val tlb = Output(new TlbCsrBundle)
-  })
+  val csrio = IO(new CSRFileIO)
   val difftestIO = IO(new Bundle() {
     val intrNO = Output(UInt(64.W))
     val cause = Output(UInt(64.W))
@@ -331,10 +341,20 @@ class CSR extends FunctionUnit with HasCSRConst
   val sscratch = RegInit(UInt(XLEN.W), 0.U)
   val scounteren = RegInit(UInt(XLEN.W), 0.U)
 
+  // spfctl Bit 0: L1plusCache Prefetcher Enable
+  // spfctl Bit 1: L2Cache Prefetcher Enable
+  val spfctl = RegInit(UInt(XLEN.W), "h3".U)
+  // sdsid: Differentiated Services ID
+  val sdsid = RegInit(UInt(XLEN.W), 0.U)
+
   val tlbBundle = Wire(new TlbCsrBundle)
   tlbBundle.satp := satp.asTypeOf(new SatpStruct)
   csrio.tlb := tlbBundle
 
+  csrio.customCtrl.l1plus_pf_enable := spfctl(0)
+  csrio.customCtrl.l2_pf_enable := spfctl(1)
+  csrio.customCtrl.dsid := sdsid
+
   // User-Level CSRs
   val uepc = Reg(UInt(XLEN.W))
 
@@ -457,6 +477,10 @@ class CSR extends FunctionUnit with HasCSRConst
     //--- Supervisor Protection and Translation ---
     MaskedRegMap(Satp, satp, satpMask, MaskedRegMap.NoSideEffect, satpMask),
 
+    //--- Supervisor Custom Read/Write Registers
+    MaskedRegMap(Spfctl, spfctl),
+    MaskedRegMap(Sdsid, sdsid),
+
     //--- Machine Information Registers ---
     MaskedRegMap(Mvendorid, mvendorid, 0.U, MaskedRegMap.Unwritable),
     MaskedRegMap(Marchid, marchid, 0.U, MaskedRegMap.Unwritable),

src/main/scala/xiangshan/backend/fu/util/CSRConst.scala

@@ -50,6 +50,11 @@ trait HasCSRConst {
   // Supervisor Protection and Translation
   val Satp          = 0x180
 
+  // Supervisor Custom Read/Write
+  val Spfctl        = 0x5C0
+
+  val Sdsid         = 0x9C0
+
   // Machine Information Registers
   val Mvendorid     = 0xF11
   val Marchid       = 0xF12

src/main/scala/xiangshan/frontend/Frontend.scala

@@ -8,7 +8,7 @@ import utils.PipelineConnect
 import xiangshan._
 import xiangshan.cache._
 import xiangshan.cache.prefetch.L1plusPrefetcher
-import xiangshan.backend.fu.HasExceptionNO
+import xiangshan.backend.fu.{HasExceptionNO, CustomCSRCtrlIO}
 
 class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter{
 
@@ -33,6 +33,7 @@ class FrontendImp (outer: Frontend) extends LazyModuleImp(outer)
     val backend = new FrontendToBackendIO
     val sfence = Input(new SfenceBundle)
     val tlbCsr = Input(new TlbCsrBundle)
+    val csrCtrl = Input(new CustomCSRCtrlIO)
   })
 
   val ifu = Module(new IFU)
@@ -72,6 +73,7 @@ class FrontendImp (outer: Frontend) extends LazyModuleImp(outer)
   io.l1plusFlush := ifu.io.l1plusFlush
   l1plusPrefetcher.io.in.valid := ifu.io.prefetchTrainReq.valid
   l1plusPrefetcher.io.in.bits := ifu.io.prefetchTrainReq.bits
+  l1plusPrefetcher.io.enable := RegNext(io.csrCtrl.l1plus_pf_enable)
   val memAcquireArb = Module(new Arbiter(new L1plusCacheReq, nClients))
   memAcquireArb.io.in(icacheMissQueueId) <> ifu.io.icacheMemAcq
   memAcquireArb.io.in(icacheMissQueueId).bits.id := Cat(icacheMissQueueId.U(clientIdWidth.W),