Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
OpenXiangShan
XiangShan
提交
b31c62ab
X
XiangShan
项目概览
OpenXiangShan
/
XiangShan
10 个月 前同步成功
通知
1183
Star
3914
Fork
526
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
DevOps
流水线
流水线任务
计划
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
X
XiangShan
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
DevOps
DevOps
流水线
流水线任务
计划
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
流水线任务
提交
Issue看板
前往新版Gitcode,体验更适合开发者的 AI 搜索 >>
提交
b31c62ab
编写于
2月 25, 2021
作者:
W
wangkaifan
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
perf: support external intervened pf-cnt clean & dump
上级
8da1d657
变更
4
隐藏空白更改
内联
并排
Showing
4 changed file
with
30 addition
and
4 deletion
+30
-4
src/main/scala/utils/LogUtils.scala
src/main/scala/utils/LogUtils.scala
+8
-1
src/main/scala/xiangshan/Bundle.scala
src/main/scala/xiangshan/Bundle.scala
+5
-0
src/main/scala/xiangshan/XSCore.scala
src/main/scala/xiangshan/XSCore.scala
+5
-1
src/test/scala/top/XSSim.scala
src/test/scala/top/XSSim.scala
+12
-2
未找到文件。
src/main/scala/utils/LogUtils.scala
浏览文件 @
b31c62ab
...
...
@@ -120,6 +120,13 @@ object XSPerf extends HasXSParameter {
if
(!
env
.
FPGAPlatform
&&
!
env
.
DualCore
)
{
ExcitingUtils
.
addSink
(
xstrap
,
"XSTRAP"
,
ConnectionType
.
Debug
)
}
val
perfClean
=
WireInit
(
false
.
B
)
val
perfDump
=
WireInit
(
false
.
B
)
ExcitingUtils
.
addSink
(
perfClean
,
"XSPERF_CLEAN"
)
ExcitingUtils
.
addSink
(
perfDump
,
"XSPERF_DUMP"
)
when
(
perfClean
)
{
counter
:=
0.
U
}
when
(
printEnable
)
{
// interval print
if
(
acc
)
{
XSLog
(
XSLogLevel
.
PERF
)(
true
,
true
.
B
,
p
"$perfName, $next_counter\n"
)
...
...
@@ -127,7 +134,7 @@ object XSPerf extends HasXSParameter {
XSLog
(
XSLogLevel
.
PERF
)(
true
,
true
.
B
,
p
"$perfName, $perfCnt\n"
)
}
}
when
(
xstrap
)
{
// summary print
when
(
xstrap
||
perfDump
)
{
// summary print
// dump acc counter by default
XSLog
(
XSLogLevel
.
PERF
)(
true
,
true
.
B
,
p
"$perfName, $next_counter\n"
)
}
...
...
src/main/scala/xiangshan/Bundle.scala
浏览文件 @
b31c62ab
...
...
@@ -515,4 +515,9 @@ class TrapIO extends XSBundle {
val
pc
=
Output
(
UInt
(
VAddrBits
.
W
))
val
cycleCnt
=
Output
(
UInt
(
XLEN
.
W
))
val
instrCnt
=
Output
(
UInt
(
XLEN
.
W
))
}
class
PerfInfoIO
extends
XSBundle
{
val
clean
=
Input
(
Bool
())
val
dump
=
Input
(
Bool
())
}
\ No newline at end of file
src/main/scala/xiangshan/XSCore.scala
浏览文件 @
b31c62ab
...
...
@@ -109,7 +109,9 @@ case class XSCoreParameters
PtwL1EntrySize
:
Int
=
16
,
PtwL2EntrySize
:
Int
=
2048
,
//(256 * 8)
NumPerfCounters
:
Int
=
16
,
NrExtIntr
:
Int
=
150
NrExtIntr
:
Int
=
150
,
PerfRealTime
:
Boolean
=
false
,
PerfIntervalBits
:
Int
=
15
)
trait
HasXSParameter
{
...
...
@@ -192,6 +194,8 @@ trait HasXSParameter {
val
PtwL2EntrySize
=
core
.
PtwL2EntrySize
val
NumPerfCounters
=
core
.
NumPerfCounters
val
NrExtIntr
=
core
.
NrExtIntr
val
PerfRealTime
=
core
.
PerfRealTime
val
PerfIntervalBits
=
core
.
PerfIntervalBits
val
instBytes
=
if
(
HasCExtension
)
2
else
4
val
instOffsetBits
=
log2Ceil
(
instBytes
)
...
...
src/test/scala/top/XSSim.scala
浏览文件 @
b31c62ab
...
...
@@ -127,6 +127,7 @@ class XSSimSoC(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
val
difftest
=
new
DiffTestIO
val
difftest2
=
new
DiffTestIO
val
logCtrl
=
new
LogCtrlIO
val
perfInfo
=
new
PerfInfoIO
val
trap
=
new
TrapIO
val
trap2
=
new
TrapIO
val
uart
=
new
UARTIO
...
...
@@ -135,6 +136,7 @@ class XSSimSoC(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
dontTouch
(
io
.
difftest
)
dontTouch
(
io
.
logCtrl
)
dontTouch
(
io
.
perfInfo
)
dontTouch
(
io
.
trap
)
dontTouch
(
io
.
uart
)
...
...
@@ -225,6 +227,13 @@ class XSSimSoC(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
ExcitingUtils
.
addSource
(
timer
,
"logTimestamp"
)
}
if
(
env
.
EnablePerfDebug
)
{
val
clean
=
io
.
perfInfo
.
clean
val
dump
=
io
.
perfInfo
.
dump
ExcitingUtils
.
addSource
(
clean
,
"XSPERF_CLEAN"
)
ExcitingUtils
.
addSource
(
dump
,
"XSPERF_DUMP"
)
}
// Check and dispaly all source and sink connections
ExcitingUtils
.
fixConnections
()
ExcitingUtils
.
checkAndDisplay
()
...
...
@@ -252,6 +261,7 @@ class XSSimTop(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
val
difftest
=
new
DiffTestIO
val
difftest2
=
new
DiffTestIO
val
logCtrl
=
new
LogCtrlIO
val
perfInfo
=
new
PerfInfoIO
val
trap
=
new
TrapIO
val
trap2
=
new
TrapIO
val
uart
=
new
UARTIO
...
...
@@ -261,6 +271,7 @@ class XSSimTop(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
io
.
difftest
<>
dut
.
module
.
io
.
difftest
io
.
logCtrl
<>
dut
.
module
.
io
.
logCtrl
io
.
perfInfo
<>
dut
.
module
.
io
.
perfInfo
io
.
trap
<>
dut
.
module
.
io
.
trap
io
.
uart
<>
dut
.
module
.
io
.
uart
if
(!
env
.
FPGAPlatform
&&
env
.
DualCore
)
{
...
...
@@ -269,8 +280,7 @@ class XSSimTop(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
}
if
(
axiSim
)
{
io
.
memAXI
<>
axiSimRam
.
module
.
io
}
else
{
}
else
{
io
.
memAXI
<>
DontCare
}
}
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录