This reverts commit 58fca539.

Log and waveform are controlled by cpu clock cycles instead of simulated cycles.
When loading from snapshot and assert stops the simulation, we cannot know the accurate cpu cycle.
To determine the actual cpu clock, we print cycleCnt when loading from snapshot.

--threads 1 can delay assert to the end of each cycle and produce the entire log

have not connected the performance counters to CSR

emu: asynchronous reset ram

We need to asynchronous reset the system when reset is true.
In verilator model, it's done by always resetting the external devices when reset is true.
After the reset signal is released, we call init once for external devices to make sure they are correctly reset.