* AXI requires araddr to be aligned with arsize

* 64-bit multiplier consumes more DSPs on FPGA than 32-bit multiplier.
  Cascaded DSPs lead to poor timing, and must improve by more registers.

debug,Makefile: add more rules

See merge request projectn/noop!12

Fix mdu

See merge request projectn/noop!11

* This will increase the latency of word operations:
  IPC: 0.544714 -> 0.528246
* Should perform more optimization on earlyFinish.

Refactor

See merge request projectn/noop!10

* IPC: 0.549364 -> 0.544714
  * on FPGA should yield better result

Rv64im

See merge request projectn/noop!9

* it seems the probe address is incorrectly shifted by 0x80 while
  probing dcache

* this let riscv-tortrue/overnight-parallel/run.py to grep the number of
  instructions in a unified manner

Makefile: fix dependency of $(REF_SO)

See merge request projectn/noop!8

Fpga pal

See merge request projectn/noop!7