- 03 3月, 2021 5 次提交
-
-
由 zhanglinjuan 提交于
-
由 ljw 提交于
-
由 zfw 提交于
* sbuffer: use plru * sbuffer: use drainIdx when drain sbuffer * Fix typo * sbuffer: set the evict threshold=12 Co-authored-by: Nljw <linjiav@outlook.com>
-
由 Steve Gou 提交于
-
由 Steve Gou 提交于
* core: enable sc * sc: calculate sum again on update * sc: clean ups * sc: add some debug info * sc, tage, bim: fix wrbypass logic, add wrbypass for SC * core: disable sc by default Co-authored-by: Njinyue110 <jinyue161@mails.ucas.ac.cn>
-
- 02 3月, 2021 2 次提交
-
-
由 ljw 提交于
* CtrlBlock: delay exception flush for 1 cycle * CtrlBlock: delay load replay for 1 cycle * roq: delay wb from exu for one clock cycle to meet timing * CtrlBlock: fix pipeline bug between decode and rename Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>
-
由 Steve Gou 提交于
-
- 01 3月, 2021 6 次提交
-
-
由 Yinan Xu 提交于
-
由 ljw 提交于
L1plus sram change
-
由 ljw 提交于
-
由 Jay 提交于
do way-allocating while writing ubtb, thus preventing multiple hits
-
由 allen 提交于
* DCache: remove ecc to improve timing. * MissQueue: refill_arb change RRArbiter to Arbiter to improve timing.
-
由 Steve Gou 提交于
add performance counters separately for each predictor component
-
- 28 2月, 2021 23 次提交
-
-
由 Lemover 提交于
* TLB: add more tlb and ptw's perf counter * TLB: change perf count signal name(rm module name)
-
由 Yinan Xu 提交于
-
由 zoujr 提交于
-
由 jinyue110 提交于
-
由 jinyue110 提交于
-
由 Lingrui98 提交于
-
由 ljw 提交于
-
由 Yinan Xu 提交于
-
由 ljw 提交于
* Ftq: use reg instead 4r_sram * Ftq: use delayed value form exu output
-
由 Lingrui98 提交于
-
由 Lingrui98 提交于
-
由 Lingrui98 提交于
-
由 jinyue110 提交于
-
由 zoujr 提交于
-
由 zoujr 提交于
-
由 wakafa 提交于
* perf: set acc arg of XSPerf as false by default * perf: add write-port competition counter for intBlock & floatBlock * perf: remove prefix of perf signal * perf: add perf-cnt for interface between frontend & backend * perf: modify perf-cnt for prefetchers
-
由 ljw 提交于
-
由 zoujr 提交于
-
由 zoujr 提交于
-
由 William Wang 提交于
* WaitTable: add waittable framework * WaitTable: get replay info from RedirectGenerator * StoreQueue: maintain issuePtr for load rs * RS: add loadWait to rs (only for load Unit's rs) * WaitTable: fix update logic * StoreQueue: fix issuePtr update logic * chore: set loadWaitBit in ibuffer * StoreQueue: fix issuePtrExt update logic Former logic does not work well with mmio logic We may also make sure that issuePtrExt is not before cmtPtrExt * WaitTable: write with priority * StoreQueue: fix issuePtrExt update logic for mmio * chore: fix typos * CSR: add slvpredctrl * slvpredctrl will control load violation predict micro architecture * WaitTable: use xor folded pc to index waittable Co-authored-by: NZhangZifei <1773908404@qq.com>
-
由 Steve Gou 提交于
-
由 Yinan Xu 提交于
* intWb: set wb.valid when !fpwen to allow writeback if !fpwen and !rfwen * RS: pass ExuConfigs instead of wake-up port number to rs * ci: add mcf, xalancbmk, gcc and namd to CI for performance test * ram: change default dram model to DRAMsim3 model * RS: store's rs's base-src dont care fp wake-up * update default configurations * rs: fix replay delay to avoid deadlock * load: fix tlb feedback * update default configurations
-
由 zoujr 提交于
-
- 27 2月, 2021 4 次提交
-
-
由 Yinan Xu 提交于
* intWb: set wb.valid when !fpwen to allow writeback if !fpwen and !rfwen * rs: fix replay delay to avoid deadlock * load: fix tlb feedback
-
由 zoujr 提交于
-
由 Lemover 提交于
* RS: pass ExuConfigs instead of wake-up port number to rs * RS: store's rs's base-src dont care fp wake-up
-
由 Yinan Xu 提交于
-