RS: store rs's base-src doesn't care fp wake-up ports (#603)

* RS: pass ExuConfigs instead of wake-up port number to rs

* RS: store's rs's base-src dont care fp wake-up

src/main/scala/xiangshan/backend/FloatBlock.scala

@@ -95,12 +95,13 @@ class FloatBlock
     }
 
     val readFpRf = cfg.readFpRf
+    val wakeUpInRecodeWithCfg = intSlowWakeUpIn.zip(intRecoded) ++ memSlowWakeUpIn.zip(memRecoded)
 
-    val inBlockWbData = exeUnits.filter(e => e.config.hasCertainLatency).map(_.io.out.bits.data)
-    val fastPortsCnt = inBlockWbData.length
+    val inBlockFastPorts = exeUnits.filter(e => e.config.hasCertainLatency).map(a => (a.config, a.io.out.bits.data))
+    val fastPortsCnt = inBlockFastPorts.length
 
-    val inBlockListenPorts = exeUnits.filter(e => e.config.hasUncertainlatency).map(_.io.out)
-    val slowPorts = (inBlockListenPorts ++ wakeUpInRecode).map(decoupledIOToValidIO)
+    val inBlockListenPorts = exeUnits.filter(e => e.config.hasUncertainlatency).map(a => (a.config, a.io.out))
+    val slowPorts = (inBlockListenPorts ++ wakeUpInRecodeWithCfg).map(a => (a._1, decoupledIOToValidIO(a._2)))
     val slowPortsCnt = slowPorts.length
 
     println(s"${i}: exu:${cfg.name} fastPortsCnt: ${fastPortsCnt} " +
@@ -108,7 +109,13 @@ class FloatBlock
       s"delay:${certainLatency}"
     )
 
-    val rs = Module(new ReservationStation(cfg, XLEN + 1, fastPortsCnt, slowPortsCnt, fixedDelay = certainLatency, fastWakeup = certainLatency >= 0, feedback = false))
+    val rs = Module(new ReservationStation(cfg, XLEN + 1,
+      inBlockFastPorts.map(_._1),
+      slowPorts.map(_._1),
+      fixedDelay = certainLatency,
+      fastWakeup = certainLatency >= 0,
+      feedback = false
+    ))
 
     rs.io.redirect <> redirect // TODO: remove it
     rs.io.flush <> flush // TODO: remove it
@@ -124,8 +131,8 @@ class FloatBlock
     rs.io.srcRegValue(1) := src2Value(readPortIndex(i))
     if (cfg.fpSrcCnt > 2) rs.io.srcRegValue(2) := src3Value(readPortIndex(i))
 
-    rs.io.fastDatas <> inBlockWbData
-    rs.io.slowPorts <> slowPorts
+    rs.io.fastDatas <> inBlockFastPorts.map(_._2)
+    rs.io.slowPorts <> slowPorts.map(_._2)
 
     exeUnits(i).io.redirect <> redirect
     exeUnits(i).io.flush <> flush
@@ -200,4 +207,4 @@ class FloatBlock
       rf.data := wb.bits.data
   }
 
-}
\ No newline at end of file
+}

src/main/scala/xiangshan/backend/IntegerBlock.scala

@@ -156,19 +156,25 @@ class IntegerBlock
 
     val readIntRf = cfg.readIntRf
 
-    val inBlockWbData = exeUnits.filter(e => e.config.hasCertainLatency).map(_.io.out.bits.data)
-    val fastDatas = inBlockWbData ++ io.wakeUpIn.fast.map(_.bits.data)
-    val wakeupCnt = fastDatas.length
+    val inBlockWbData = exeUnits.filter(e => e.config.hasCertainLatency).map(a => (a.config, a.io.out.bits.data))
+    val fastDatas = inBlockWbData ++ fastWakeUpIn.zip(io.wakeUpIn.fast.map(_.bits.data))
+    val fastPortsCnt = fastDatas.length
 
-    val inBlockListenPorts = exeUnits.filter(e => e.config.hasUncertainlatency).map(_.io.out)
-    val slowPorts = (inBlockListenPorts ++ io.wakeUpIn.slow).map(decoupledIOToValidIO)
+    val inBlockListenPorts = exeUnits.filter(e => e.config.hasUncertainlatency).map(a => (a.config, a.io.out))
+    val slowPorts = (inBlockListenPorts ++ slowWakeUpIn.zip(io.wakeUpIn.slow)).map(a => (a._1, decoupledIOToValidIO(a._2)))
     val extraListenPortsCnt = slowPorts.length
 
     val feedback = (cfg == ldExeUnitCfg) || (cfg == stExeUnitCfg)
 
-    println(s"${i}: exu:${cfg.name} wakeupCnt: ${wakeupCnt} slowPorts: ${extraListenPortsCnt} delay:${certainLatency} feedback:${feedback}")
+    println(s"${i}: exu:${cfg.name} fastPortsCnt: ${fastPortsCnt} slowPorts: ${extraListenPortsCnt} delay:${certainLatency} feedback:${feedback}")
 
-    val rs = Module(new ReservationStation(cfg, XLEN + 1, wakeupCnt, extraListenPortsCnt, fixedDelay = certainLatency, fastWakeup = certainLatency >= 0, feedback = feedback))
+    val rs = Module(new ReservationStation(cfg, XLEN + 1,
+      fastDatas.map(_._1),
+      slowPorts.map(_._1),
+      fixedDelay = certainLatency,
+      fastWakeup = certainLatency >= 0,
+      feedback = feedback
+    ))
 
     rs.io.redirect <> redirect
     rs.io.flush <> flush // TODO: remove it
@@ -185,8 +191,8 @@ class IntegerBlock
       rs.io.jalr_target := io.fromCtrlBlock.jalr_target
     }
 
-    rs.io.fastDatas <> fastDatas
-    rs.io.slowPorts <> slowPorts
+    rs.io.fastDatas <> fastDatas.map(_._2)
+    rs.io.slowPorts <> slowPorts.map(_._2)
 
     exeUnits(i).io.redirect <> redirect
     exeUnits(i).io.fromInt <> rs.io.deq

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -137,11 +137,10 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
     // load has uncertain latency, so only use external wake up data
     val fastDatas = fastWakeUpIn.zip(io.wakeUpIn.fast)
       .filter(x => (x._1.writeIntRf && readIntRf) || (x._1.writeFpRf && readFpRf))
-      .map(_._2.bits.data)
-    val wakeupCnt = fastDatas.length
+    val fastPortsCnt = fastDatas.length
 
     val slowPorts = (
-      (if(cfg == Exu.stExeUnitCfg) wakeUpFp else exeWbReqs) ++
+      (loadExuConfigs.zip(if(cfg == Exu.stExeUnitCfg) wakeUpFp else exeWbReqs)) ++
       slowWakeUpIn.zip(io.wakeUpIn.slow)
         .filter(x => (x._1.writeIntRf && readIntRf) || (x._1.writeFpRf && readFpRf))
         .map{
@@ -152,19 +151,25 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
               value.valid && !value.bits.uop.roqIdx.needFlush(redirect, io.fromCtrlBlock.flush)
             )
             jumpOut.ready := true.B
-            jumpOut
-          case (_, value) => value
+            (Exu.jumpExeUnitCfg, jumpOut)
+          case (config, value) => (config, value)
         }
-      ).map(decoupledIOToValidIO)
+    ).map(a => (a._1, decoupledIOToValidIO(a._2)))
 
     val slowPortsCnt = slowPorts.length
 
     // if tlb miss, replay
     val feedback = true
 
-    println(s"${i}: exu:${cfg.name} wakeupCnt: ${wakeupCnt} slowPorts: ${slowPortsCnt} delay:${certainLatency} feedback:${feedback}")
+    println(s"${i}: exu:${cfg.name} fastPortsCnt: ${fastPortsCnt} slowPorts: ${slowPortsCnt} delay:${certainLatency} feedback:${feedback}")
 
-    val rs = Module(new ReservationStation(cfg, XLEN + 1, wakeupCnt, slowPortsCnt, fixedDelay = certainLatency, fastWakeup = certainLatency >= 0, feedback = feedback))
+    val rs = Module(new ReservationStation(cfg, XLEN + 1,
+      fastDatas.map(_._1),
+      slowPorts.map(_._1),
+      fixedDelay = certainLatency,
+      fastWakeup = certainLatency >= 0,
+      feedback = feedback)
+    )
 
     rs.io.redirect <> redirect // TODO: remove it
     rs.io.flush    <> io.fromCtrlBlock.flush // TODO: remove it
@@ -177,8 +182,8 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
       rs.io.fpRegValue := io.fromFpBlock.readFpRf(i - exuParameters.LduCnt).data
     }
 
-    rs.io.fastDatas <> fastDatas
-    rs.io.slowPorts <> slowPorts
+    rs.io.fastDatas <> fastDatas.map(_._2.bits.data)
+    rs.io.slowPorts <> slowPorts.map(_._2)
 
     // exeUnits(i).io.redirect <> redirect
     // exeUnits(i).io.fromInt <> rs.io.deq

src/main/scala/xiangshan/backend/issue/ReservationStation.scala

@@ -83,8 +83,8 @@ class ReservationStation
 (
   val exuCfg: ExuConfig,
   srcLen: Int,
-  fastPortsCnt: Int,
-  slowPortsCnt: Int,
+  fastPortsCfg: Seq[ExuConfig],
+  slowPortsCfg: Seq[ExuConfig],
   fixedDelay: Int,
   fastWakeup: Boolean,
   feedback: Boolean,
@@ -93,6 +93,8 @@ class ReservationStation
   val iqIdxWidth = log2Up(iqSize)
   val nonBlocked = fixedDelay >= 0
   val srcNum = if (exuCfg == Exu.jumpExeUnitCfg) 2 else max(exuCfg.intSrcCnt, exuCfg.fpSrcCnt)
+  val fastPortsCnt = fastPortsCfg.size
+  val slowPortsCnt = slowPortsCfg.size
   require(nonBlocked==fastWakeup)
 
   val io = IO(new Bundle {
@@ -115,9 +117,9 @@ class ReservationStation
     val rsIdx = if (feedback) Output(UInt(log2Up(IssQueSize).W)) else null
   })
 
-  val select = Module(new ReservationStationSelect(exuCfg, srcLen, fastPortsCnt, slowPortsCnt, fixedDelay, fastWakeup, feedback))
-  val ctrl   = Module(new ReservationStationCtrl(exuCfg, srcLen, fastPortsCnt, slowPortsCnt, fixedDelay, fastWakeup, feedback))
-  val data   = Module(new ReservationStationData(exuCfg, srcLen, fastPortsCnt, slowPortsCnt, fixedDelay, fastWakeup, feedback))
+  val select = Module(new ReservationStationSelect(exuCfg, srcLen, fastPortsCfg, slowPortsCfg, fixedDelay, fastWakeup, feedback))
+  val ctrl   = Module(new ReservationStationCtrl(exuCfg, srcLen, fastPortsCfg, slowPortsCfg, fixedDelay, fastWakeup, feedback))
+  val data   = Module(new ReservationStationData(exuCfg, srcLen, fastPortsCfg, slowPortsCfg, fixedDelay, fastWakeup, feedback))
 
   select.io.redirect := io.redirect
   select.io.flush := io.flush
@@ -184,17 +186,18 @@ class ReservationStationSelect
 (
   val exuCfg: ExuConfig,
   srcLen: Int,
-  fastPortsCnt: Int,
-  slowPortsCnt: Int,
+  fastPortsCfg: Seq[ExuConfig],
+  slowPortsCfg: Seq[ExuConfig],
   fixedDelay: Int,
   fastWakeup: Boolean,
   feedback: Boolean,
 ) extends XSModule with HasCircularQueuePtrHelper{
-
   val iqSize = IssQueSize
   val iqIdxWidth = log2Up(iqSize)
   val nonBlocked = fixedDelay >= 0
   val srcNum = if (exuCfg == Exu.jumpExeUnitCfg) 2 else max(exuCfg.intSrcCnt, exuCfg.fpSrcCnt)
+  val fastPortsCnt = fastPortsCfg.size
+  val slowPortsCnt = slowPortsCfg.size
   require(nonBlocked==fastWakeup)
   val delayMap = Map(
     0 -> 5,
@@ -376,17 +379,18 @@ class ReservationStationCtrl
 (
   val exuCfg: ExuConfig,
   srcLen: Int,
-  fastPortsCnt: Int,
-  slowPortsCnt: Int,
+  fastPortsCfg: Seq[ExuConfig],
+  slowPortsCfg: Seq[ExuConfig],
   fixedDelay: Int,
   fastWakeup: Boolean,
   feedback: Boolean,
 ) extends XSModule {
-
   val iqSize = IssQueSize
   val iqIdxWidth = log2Up(iqSize)
   val nonBlocked = fixedDelay >= 0
   val srcNum = if (exuCfg == Exu.jumpExeUnitCfg) 2 else max(exuCfg.intSrcCnt, exuCfg.fpSrcCnt)
+  val fastPortsCnt = fastPortsCfg.size
+  val slowPortsCnt = slowPortsCfg.size
   require(nonBlocked==fastWakeup)
 
   val io = IO(new XSBundle {
@@ -446,7 +450,11 @@ class ReservationStationCtrl
   srcUpdateListen.map(a => a.map(b => b.map(c => c := false.B )))
   for (i <- 0 until iqSize) {
     for (j <- 0 until srcNum) {
-      srcUpdate(i)(j) := Cat(srcUpdateListen(i)(j)).orR
+      if (exuCfg == Exu.stExeUnitCfg && j == 0) {
+        srcUpdate(i)(j) := Cat(srcUpdateListen(i)(j).zip(fastPortsCfg ++ slowPortsCfg).filter(_._2.writeIntRf).map(_._1)).orR
+      } else {
+        srcUpdate(i)(j) := Cat(srcUpdateListen(i)(j)).orR
+      }
     }
   }
 
@@ -647,8 +655,8 @@ class ReservationStationData
 (
   val exuCfg: ExuConfig,
   srcLen: Int,
-  fastPortsCnt: Int,
-  slowPortsCnt: Int,
+  fastPortsCfg: Seq[ExuConfig],
+  slowPortsCfg: Seq[ExuConfig],
   fixedDelay: Int,
   fastWakeup: Boolean,
   feedback: Boolean,
@@ -657,9 +665,10 @@ class ReservationStationData
   val iqIdxWidth = log2Up(iqSize)
   val nonBlocked = fixedDelay >= 0
   val srcNum = if (exuCfg == Exu.jumpExeUnitCfg) 2 else max(exuCfg.intSrcCnt, exuCfg.fpSrcCnt)
+  val fastPortsCnt = fastPortsCfg.size
+  val slowPortsCnt = slowPortsCfg.size
   require(nonBlocked==fastWakeup)
 
-
   val io = IO(new XSBundle {
     val srcRegValue = Vec(srcNum, Input(UInt(srcLen.W)))
     val fpRegValue = if (exuCfg == Exu.stExeUnitCfg) Input(UInt(srcLen.W)) else null
@@ -687,7 +696,8 @@ class ReservationStationData
   // Data : single read, multi write
   // ------------------------
   val data = if (exuCfg == Exu.stExeUnitCfg) {
-    val srcBase = Module(new RSDataSingleSrc(srcLen, iqSize, fastPortsCnt + slowPortsCnt, 1))
+    val baseListenWidth = (fastPortsCfg ++ slowPortsCfg).filter(_.writeIntRf).size
+    val srcBase = Module(new RSDataSingleSrc(srcLen, iqSize, baseListenWidth, 1))
     val srcData = Module(new RSDataSingleSrc(srcLen, iqSize, fastPortsCnt + slowPortsCnt, 2))
     srcBase.suggestName(s"${this.name}_data0")
     srcData.suggestName(s"${this.name}_data1")
@@ -700,8 +710,13 @@ class ReservationStationData
     }
   }
   (0 until srcNum).foreach{ i =>
-    data(i).listen.wen := io.listen.wen(i)
-    data(i).listen.wdata := io.listen.wdata
+    if (exuCfg == Exu.stExeUnitCfg && i == 0) {
+      data(i).listen.wen := VecInit(io.listen.wen(i).map(a => VecInit(a.zip((fastPortsCfg ++ slowPortsCfg).map(_.writeIntRf)).filter(_._2).map(_._1))))
+      data(i).listen.wdata := io.listen.wdata.zip((fastPortsCfg ++ slowPortsCfg).map(_.writeIntRf)).filter(_._2).map(_._1)
+    } else {
+      data(i).listen.wen := io.listen.wen(i)
+      data(i).listen.wdata := io.listen.wdata
+    }
   }
 
   val addrReg = RegEnable(io.in.addr, io.in.valid)