TLB: add more tlb and ptw's performance counters (#610)

* TLB: add more tlb and ptw's perf counter

* TLB: change perf count signal name(rm module name)

src/main/scala/xiangshan/cache/PTW.scala

@@ -716,6 +716,15 @@ class PTWImp(outer: PTW) extends PtwModule(outer) {
     }
   }
 
+  // Perf Count
+  XSPerf("access", validOneCycle)
+  XSPerf("l1_hit", l1Hit)
+  XSPerf("l2_hit", l2Hit)
+  XSPerf("l3_hit", l3Hit)
+  XSPerf("mem_count", memReqFire)
+  XSPerf("mem_cycle", BoolStopWatch(memReqFire, memRespFire, true))
+  XSPerf("mem_blocked_cycle", mem.a.valid && !memReqReady)
+
   // debug info
   for (i <- 0 until PtwWidth) {
     XSDebug(p"[io.tlb(${i.U})] ${io.tlb(i)}\n")
@@ -726,7 +735,7 @@ class PTWImp(outer: PTW) extends PtwModule(outer) {
   XSDebug(p"req:${req} arb.io.out:(${arb.io.out.valid},${arb.io.out.ready}) arbChosen:${arbChosen} ptwFinish:${ptwFinish}\n")
 
   XSDebug(p"[mem][A] (${mem.a.valid},${mem.a.ready})\n")
-  XSDebug(p"[mem][A] memAddr:0x${Hexadecimal(memAddr)} l1addr:0x${Hexadecimal(l1addr)} l2addr:0x${Hexadecimal(l2addr)} l3addr:0x${Hexadecimal(l3addr)} memAddrReg:0x${Hexadecimal(memAddrReg)} memPteReg.ppn:0x${Hexadecimal(memPteReg.ppn)}")
+  XSDebug("[mem][A] memAddr:0x${Hexadecimal(memAddr)} l1addr:0x${Hexadecimal(l1addr)} l2addr:0x${Hexadecimal(l2addr)} l3addr:0x${Hexadecimal(l3addr)} memAddrReg:0x${Hexadecimal(memAddrReg)} memPteReg.ppn:0x${Hexadecimal(memPteReg.ppn)}")
   XSDebug(p"[mem][D] (${mem.d.valid},${mem.d.ready}) memSelData:0x${Hexadecimal(memSelData)} memPte:${memPte} memPte.isLeaf:${memPte.isLeaf()} memPte.isPf(${level}):${memPte.isPf(level)}\n")
   XSDebug(memRespFire, p"[mem][D] memPtes:${printVec(memPtes)}\n")
 
@@ -771,4 +780,4 @@ class PTWRepeater extends XSModule with HasXSParameter with HasXSLog with HasPtw
   XSDebug(io.tlb.req.valid || io.tlb.resp.valid, p"tlb: ${tlb}\n")
   XSDebug(io.ptw.req.valid || io.ptw.resp.valid, p"ptw: ${ptw}\n")
   assert(!RegNext(recv && io.ptw.resp.valid), "re-receive ptw.resp")
-}
\ No newline at end of file
+}

src/main/scala/xiangshan/cache/TLB.scala

@@ -532,9 +532,17 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
     for (i <- 0 until Width) {
       XSPerf("miss" + Integer.toString(i, 10), valid(i) && vmEnable && missVec(i))
     }
+    XSPerf("ptw_req_count", ptw.req.fire())
+    XSPerf("ptw_req_cycle", waiting)
+    XSPerf("wait_blocked_count", waiting && hasMissReq)
+    XSPerf("ptw_resp_pf_count", ptw.resp.fire() && ptw.resp.bits.pf)
   } else {
     XSPerf("access", valid(0) && vmEnable)
     XSPerf("miss", valid(0) && vmEnable && missVec(0))
+    XSPerf("ptw_req_count", ptw.req.fire())
+    XSPerf("ptw_req_cycle", waiting)
+    XSPerf("wait_blocked_count", waiting && hasMissReq)
+    XSPerf("ptw_resp_pf_count", ptw.resp.fire() && ptw.resp.bits.pf)
   }
 
   // Log