FPUv0.1 can pass all rvf/rvd tests in both riscv-tests and berkeley-softfloat
Signed-off-by: NLinJiawei <linjiav@outlook.com>

* NOTE: if we fetch and execute a store instruction from MMIO, currently
  DiffTest can not handle this situation.

fix bug: pipeline doesn't fit tlb when vmEnble turns from 0 to 1. add to vmEnable signal to new PipelineConnectTLB

cancel fu.tlb, move sfence_vma decode to fu.mou && cancel TLBEXUIO, turn to BoringUtils.addSink/addSource

add instr sfence.vma && add sfence_vma at nanos-lite/schedule() && add priv 0x120 at nemu/make_EHelper(priv) && passed nanos-lite/xianjian

* When executing fence.i, the pipeline and ICache will be flushed. New
  instructions will be fetched from memory, or DCache with coherence
  support.
* With fence.i, we should pass nexus-am/tests/cachetest/test/loader.c.

* SimpleBusUL is used for MMIO and SimpleBusUH is used for memory
* should refactor SimpleBus2AXI4Converter to support SimpleBusUL and
  SimpleBusUH

This reverts commit 89b7c53e.

* Some small functions will return quickly. `ret` is executed without
  the correct return address pushed into RAS.

* ultraZ gives better performance than zedboard