noop,EXU: merge original BRU to ALU

src/main/scala/noop/BPU.scala

@@ -35,7 +35,7 @@ class BPUUpdateReq extends Bundle {
   val isMissPredict = Output(Bool())
   val actualTarget = Output(UInt(32.W))
   val actualTaken = Output(Bool())  // for branch
-  val fuOpType = Output(UInt(4.W))
+  val fuOpType = Output(UInt(5.W))
   val btbType = Output(BTBtype())
 }
 

src/main/scala/noop/Decode.scala

@@ -37,17 +37,13 @@ trait HasFuType
     with HasLSUOpType
     with HasMDUOpType
     with HasCSROpType {
-  val FuTypeNum = 5
-  def FuAlu = "b000".U
-  def FuBru = "b001".U
-  def FuLsu = "b010".U
-  def FuMdu = "b011".U
-  def FuCsr = "b100".U
+  val FuTypeNum = 4
+  def FuAlu = "b00".U
+  def FuLsu = "b01".U
+  def FuMdu = "b10".U
+  def FuCsr = "b11".U
   val FuTypeWidth = log2Up(FuTypeNum).W
-
-  private val FuOpTypeMaxNum = List(AluOpTypeNum, BruOpTypeNum,
-    LsuOpTypeNum, MduOpTypeNum, CsrOpTypeNum).reduce(math.max)
-  val FuOpTypeWidth = log2Up(FuOpTypeMaxNum).W
+  val FuOpTypeWidth = 5.W
 }
 
 trait HasDecodeConst extends HasInstrType with HasSrcType with HasFuType

src/main/scala/noop/EXU.scala

@@ -16,7 +16,6 @@ class EXU(implicit val p: NOOPConfig) extends Module with HasFuType {
     val mmio = new SimpleBus
     val forward = new ForwardIO
     val wbData = Input(UInt(32.W))
-    val bpu1Update = Output(new BRUIO)
   })
 
   val src1 = io.in.bits.data.src1
@@ -29,16 +28,11 @@ class EXU(implicit val p: NOOPConfig) extends Module with HasFuType {
 
   val alu = Module(new ALU)
   val aluOut = alu.access(valid = fuValids(FuAlu), src1 = src1, src2 = src2, func = fuOpType)
+  alu.io.pc := io.in.bits.pc
+  alu.io.npc := io.in.bits.npc
+  alu.io.offset := io.in.bits.data.imm
   alu.io.out.ready := true.B
 
-  val bru = Module(new BRU)
-  val bruOut = bru.access(valid = fuValids(FuBru), src1 = src1, src2 = src2, func = fuOpType)
-  bru.io.pc := io.in.bits.pc
-  bru.io.offset := io.in.bits.data.imm
-  bru.io.npc := io.in.bits.npc
-  bru.io.out.ready := true.B
-  io.bpu1Update := bru.io
-
   val lsu = Module(new LSU)
   val lsuOut = lsu.access(valid = fuValids(FuLsu), src1 = src1, src2 = io.in.bits.data.imm, func = fuOpType)
   lsu.io.wdata := src2
@@ -57,7 +51,7 @@ class EXU(implicit val p: NOOPConfig) extends Module with HasFuType {
   csr.io.isInvOpcode := io.in.bits.ctrl.isInvOpcode
   csr.io.out.ready := true.B
 
-  io.out.bits.br <> Mux(csr.io.csrjmp.isTaken, csr.io.csrjmp, bru.io.branch)
+  io.out.bits.br <> Mux(csr.io.csrjmp.isTaken, csr.io.csrjmp, alu.io.branch)
 
   io.out.bits.ctrl := DontCare
   (io.out.bits.ctrl, io.in.bits.ctrl) match { case (o, i) =>
@@ -74,7 +68,6 @@ class EXU(implicit val p: NOOPConfig) extends Module with HasFuType {
 
   io.out.bits.commits := DontCare
   io.out.bits.commits(FuAlu).rfWdata := aluOut
-  io.out.bits.commits(FuBru).rfWdata := bruOut
   io.out.bits.commits(FuLsu).rfWdata := lsuOut
   io.out.bits.commits(FuCsr).rfWdata := csrOut
   io.out.bits.commits(FuMdu).rfWdata := mduOut
@@ -87,8 +80,8 @@ class EXU(implicit val p: NOOPConfig) extends Module with HasFuType {
   io.forward.fuType := io.in.bits.ctrl.fuType
   io.forward.rfData := Mux(alu.io.out.fire(), aluOut, lsuOut)
 
-  BoringUtils.addSource(alu.io.out.fire(), "perfCntCondMaluInstr")
-  BoringUtils.addSource(bru.io.out.fire(), "perfCntCondMbruInstr")
+  BoringUtils.addSource(alu.io.out.fire() && !isBru(fuOpType), "perfCntCondMaluInstr")
+  BoringUtils.addSource(alu.io.out.fire() && isBru(fuOpType), "perfCntCondMbruInstr")
   BoringUtils.addSource(lsu.io.out.fire(), "perfCntCondMlsuInstr")
   BoringUtils.addSource(mdu.io.out.fire(), "perfCntCondMmduInstr")
   BoringUtils.addSource(csr.io.out.fire(), "perfCntCondMcsrInstr")

src/main/scala/noop/IDU.scala

@@ -48,7 +48,7 @@ class IDU(implicit val p: NOOPConfig) extends Module with HasDecodeConst {
     InstrJ -> Cat(Fill(12, instr(31)), instr(19, 12), instr(20), instr(30, 21), 0.U(1.W))
   ))
 
-  when (fuType === FuBru) {
+  when (fuType === FuAlu) {
     when (rd === 1.U && fuOpType === BruJal) { io.out.bits.ctrl.fuOpType := BruCall }
     when (rs === 1.U && fuOpType === BruJalr) { io.out.bits.ctrl.fuOpType := BruRet }
   }

src/main/scala/noop/fu/ALU.scala

@@ -2,23 +2,24 @@ package noop
 
 import chisel3._
 import chisel3.util._
+import chisel3.util.experimental.BoringUtils
 
 import utils._
 
 trait HasALUOpType {
   val AluOpTypeNum  = 11
 
-  def AluAdd  = "b0000".U
-  def AluSll  = "b0001".U
-  def AluSlt  = "b0010".U
-  def AluSltu = "b0011".U
-  def AluXor  = "b0100".U
-  def AluSrl  = "b0101".U
-  def AluOr   = "b0110".U
-  def AluAnd  = "b0111".U
-  def AluSub  = "b1000".U
-  def AluSra  = "b1101".U
-  def AluLui  = "b1111".U
+  def AluAdd  = "b00000".U
+  def AluSll  = "b00001".U
+  def AluSlt  = "b00010".U
+  def AluSltu = "b00011".U
+  def AluXor  = "b00100".U
+  def AluSrl  = "b00101".U
+  def AluOr   = "b00110".U
+  def AluAnd  = "b00111".U
+  def AluSub  = "b01000".U
+  def AluSra  = "b01101".U
+  def AluLui  = "b01111".U
 }
 
 object ALUInstr extends HasDecodeConst {
@@ -73,8 +74,15 @@ object ALUInstr extends HasDecodeConst {
   )
 }
 
-class ALU extends Module with HasALUOpType {
-  val io = IO(new FunctionUnitIO)
+class ALUIO extends FunctionUnitIO {
+  val pc = Input(UInt(32.W))
+  val npc = Input(UInt(32.W))
+  val offset = Input(UInt(32.W))
+  val branch = new BranchIO
+}
+
+class ALU extends Module with HasALUOpType with HasBRUOpType {
+  val io = IO(new ALUIO)
 
   val (valid, src1, src2, func) = (io.in.valid, io.in.bits.src1, io.in.bits.src2, io.in.bits.func)
   def access(valid: Bool, src1: UInt, src2: UInt, func: UInt): UInt = {
@@ -85,14 +93,16 @@ class ALU extends Module with HasALUOpType {
     io.out.bits
   }
 
-  val isAdderSub = (func =/= AluAdd)
+  val isAdderSub = (func =/= AluAdd) && !isJump(func)
   val adderRes = (src1 +& (src2 ^ Fill(32, isAdderSub))) + isAdderSub
   val xorRes = src1 ^ src2
   val sltu = !adderRes(32)
   val slt = xorRes(31) ^ sltu
 
   val shamt = src2(4, 0)
-  io.out.bits := LookupTree(func, 0.U, List(
+  val aluRes = LookupTree(func, 0.U, List(
+    BruJal  -> adderRes,
+    BruJalr -> adderRes,
     AluAdd  -> adderRes,
     AluSll  -> ((src1  << shamt)(31, 0)),
     AluSlt  -> Cat(0.U(31.W), slt),
@@ -106,6 +116,42 @@ class ALU extends Module with HasALUOpType {
     AluSra  -> ((src1.asSInt >> shamt).asUInt)
   ))
 
+  val branchOpTable = List(
+    getBranchType(BruBeq)  -> (src1 === src2),
+    getBranchType(BruBlt)  -> (src1.asSInt < src2.asSInt),
+    getBranchType(BruBltu) -> (src1 < src2)
+  )
+
+  val taken = LookupTree(getBranchType(func), false.B, branchOpTable) ^ isBranchInvert(func)
+  val target = Mux(isBranch(func), io.pc + io.offset, adderRes)
+  io.branch.target := Mux(!taken && isBranch(func), io.pc + 4.U, target)
+  // with branch predictor, this is actually to fix the wrong prediction
+  io.branch.isTaken := valid && isBru(func) && (io.branch.target =/= io.npc)
+  // may be can move to ISU to calculate pc + 4
+  io.out.bits := Mux(isBru(func), io.pc + 4.U, aluRes)
+
   io.in.ready := true.B
   io.out.valid := valid
+
+  val bpuUpdateReq = WireInit(0.U.asTypeOf(new BPUUpdateReq))
+  bpuUpdateReq.valid := valid && isBru(func)
+  bpuUpdateReq.pc := io.pc
+  bpuUpdateReq.isMissPredict := io.branch.target =/= io.npc
+  bpuUpdateReq.actualTarget := target
+  bpuUpdateReq.actualTaken := taken
+  bpuUpdateReq.fuOpType := func
+  bpuUpdateReq.btbType := LookupTree(func, BRUInstr.bruFuncTobtbTypeTable)
+
+  BoringUtils.addSource(RegNext(bpuUpdateReq), "bpuUpdateReq")
+
+  val right = valid && isBru(func) && (io.npc === io.branch.target)
+  val wrong = valid && isBru(func) && (io.npc =/= io.branch.target)
+  BoringUtils.addSource(right && isBranch(func), "MbpBRight")
+  BoringUtils.addSource(wrong && isBranch(func), "MbpBWrong")
+  BoringUtils.addSource(right && (func === BruJal || func === BruCall), "MbpJRight")
+  BoringUtils.addSource(wrong && (func === BruJal || func === BruCall), "MbpJWrong")
+  BoringUtils.addSource(right && func === BruJalr, "MbpIRight")
+  BoringUtils.addSource(wrong && func === BruJalr, "MbpIWrong")
+  BoringUtils.addSource(right && func === BruRet, "MbpRRight")
+  BoringUtils.addSource(wrong && func === BruRet, "MbpRWrong")
 }

src/main/scala/noop/fu/BRU.scala

@@ -9,20 +9,22 @@ import utils._
 trait HasBRUOpType {
   val BruOpTypeNum  = 10
 
-  def BruJal  = "b1000".U
-  def BruJalr = "b1010".U
-  def BruBeq  = "b0000".U
-  def BruBne  = "b0001".U
-  def BruBlt  = "b0100".U
-  def BruBge  = "b0101".U
-  def BruBltu = "b0110".U
-  def BruBgeu = "b0111".U
+  def BruJal  = "b11000".U
+  def BruJalr = "b11010".U
+  def BruBeq  = "b10000".U
+  def BruBne  = "b10001".U
+  def BruBlt  = "b10100".U
+  def BruBge  = "b10101".U
+  def BruBltu = "b10110".U
+  def BruBgeu = "b10111".U
 
   // for RAS
-  def BruCall = "b1100".U
-  def BruRet  = "b1110".U
+  def BruCall = "b11100".U
+  def BruRet  = "b11110".U
 
+  def isBru(func: UInt) = func(4)
   def isBranch(func: UInt) = !func(3)
+  def isJump(func: UInt) = isBru(func) && !isBranch(func)
   def getBranchType(func: UInt) = func(2, 1)
   def isBranchInvert(func: UInt) = func(0)
 }
@@ -39,15 +41,15 @@ object BRUInstr extends HasDecodeConst {
   def BGEU    = BitPat("b???????_?????_?????_111_?????_1100011")
 
   val table = Array(
-    JAL            -> List(InstrJ, FuBru, BruJal),
-    JALR           -> List(InstrI, FuBru, BruJalr),
-
-    BEQ            -> List(InstrB, FuBru, BruBeq),
-    BNE            -> List(InstrB, FuBru, BruBne),
-    BLT            -> List(InstrB, FuBru, BruBlt),
-    BGE            -> List(InstrB, FuBru, BruBge),
-    BLTU           -> List(InstrB, FuBru, BruBltu),
-    BGEU           -> List(InstrB, FuBru, BruBgeu)
+    JAL            -> List(InstrJ, FuAlu, BruJal),
+    JALR           -> List(InstrI, FuAlu, BruJalr),
+
+    BEQ            -> List(InstrB, FuAlu, BruBeq),
+    BNE            -> List(InstrB, FuAlu, BruBne),
+    BLT            -> List(InstrB, FuAlu, BruBlt),
+    BGE            -> List(InstrB, FuAlu, BruBge),
+    BLTU           -> List(InstrB, FuAlu, BruBltu),
+    BGEU           -> List(InstrB, FuAlu, BruBgeu)
   )
 
   val bruFuncTobtbTypeTable = List(