noop: use exceptionVec to propagate exception signals

src/main/scala/noop/Bundle.scala

@@ -12,7 +12,6 @@ class CtrlSignalIO extends NOOPBundle {
   val rfSrc2 = Output(UInt(5.W))
   val rfWen = Output(Bool())
   val rfDest = Output(UInt(5.W))
-  val isInvOpcode = Output(Bool())
   val isNoopTrap = Output(Bool())
   val isSrc1Forward = Output(Bool())
   val isSrc2Forward = Output(Bool())
@@ -34,6 +33,7 @@ class CtrlFlowIO extends NOOPBundle {
   val pc = Output(UInt(AddrBits.W))
   val pnpc = Output(UInt(AddrBits.W))
   val redirect = new RedirectIO
+  val exceptionVec = Output(Vec(16, Bool()))
 }
 
 class DecodeIO extends NOOPBundle {

src/main/scala/noop/Decode.scala

@@ -38,7 +38,7 @@ object FuOpType {
 
 object Instructions extends HasInstrType with HasNOOPParameter {
   def NOP = 0x00000013.U
-  val DecodeDefault = List(InstrN, FuType.csr, CSROpType.jmp)
+  val DecodeDefault = List(InstrN, FuType.alu, ALUOpType.add)
   def DecodeTable = RVIInstr.table ++ NOOPTrap.table ++
     (if (HasMExtension) RVMInstr.table else Nil) ++
     RVZicsrInstr.table ++ RVZifenceiInstr.table

src/main/scala/noop/EXU.scala

@@ -51,7 +51,7 @@ class EXU(implicit val p: NOOPConfig) extends NOOPModule {
   val csr = Module(new CSR)
   val csrOut = csr.access(valid = fuValids(FuType.csr), src1 = src1, src2 = src2, func = fuOpType)
   csr.io.cfIn := io.in.bits.cf
-  csr.io.isInvOpcode := io.in.bits.ctrl.isInvOpcode
+  csr.io.instrValid := io.in.valid && !io.flush
   csr.io.out.ready := true.B
 
   val mou = Module(new MOU)

src/main/scala/noop/IDU.scala

@@ -64,7 +64,9 @@ class IDU extends NOOPModule with HasInstrType {
 
   io.out.bits.cf <> io.in.bits
 
-  io.out.bits.ctrl.isInvOpcode := (instrType === InstrN) && io.in.valid
+  io.out.bits.cf.exceptionVec.map(_ := false.B)
+  io.out.bits.cf.exceptionVec(illegalInstr) := (instrType === InstrN) && io.in.valid
+  io.out.bits.cf.exceptionVec(ecallM) := (instr === RVZicsrInstr.ECALL) && io.in.valid
   io.out.bits.ctrl.isNoopTrap := (instr === NOOPTrap.TRAP) && io.in.valid
   io.out.valid := io.in.valid
 

src/main/scala/noop/NOOP.scala

@@ -20,7 +20,7 @@ trait HasNOOPParameter {
   val DataBytes = DataBits / 8
 }
 
-abstract class NOOPModule extends Module with HasNOOPParameter
+abstract class NOOPModule extends Module with HasNOOPParameter with HasExceptionNO
 abstract class NOOPBundle extends Bundle with HasNOOPParameter
 
 case class NOOPConfig (

src/main/scala/noop/fu/CSR.scala

@@ -25,11 +25,28 @@ trait HasCSRConst {
   def privMret  = 0x302.U
 }
 
+trait HasExceptionNO {
+  def instrAddrMisaligned = 0
+  def instrAccessFault    = 1
+  def illegalInstr        = 2
+  def breakPoint          = 3
+  def loadAddrMisaligned  = 4
+  def loadAccessFault     = 5
+  def storeAddrMisaligned = 6
+  def storeAccessFault    = 7
+  def ecallU              = 8
+  def ecallS              = 9
+  def ecallM              = 11
+  def instrPageFault      = 12
+  def loadPageFault       = 13
+  def storePageFault      = 15
+}
+
 class CSRIO extends FunctionUnitIO {
   val cfIn = Flipped(new CtrlFlowIO)
   val redirect = new RedirectIO
-  // exception
-  val isInvOpcode = Input(Bool())
+  // for exception check
+  val instrValid = Input(Bool())
 }
 
 class CSR(implicit val p: NOOPConfig) extends NOOPModule with HasCSRConst {
@@ -124,16 +141,12 @@ class CSR(implicit val p: NOOPConfig) extends NOOPModule with HasCSRConst {
   io.out.bits := rdata
 
   val isMret = addr === privMret
-  val raiseException = (io.isInvOpcode && valid) || raiseIntr
-  val isEcall = (addr === privEcall) && !raiseException
-  val exceptionNO = Mux1H(List(
-    io.isInvOpcode -> 2.U,
-    isEcall -> 11.U
-  ))
+  val raiseException = io.cfIn.exceptionVec.asUInt.orR && io.instrValid
+  val exceptionNO = PriorityEncoder(io.cfIn.exceptionVec)
   val intrNO = PriorityEncoder(intrVec) // FIXME: check this
   val causeNO = (raiseIntr << (XLEN-1)) | Mux(raiseIntr, intrNO, exceptionNO)
 
-  io.redirect.valid := (valid && func === CSROpType.jmp) || raiseException
+  io.redirect.valid := (valid && func === CSROpType.jmp) || raiseException || raiseIntr
   io.redirect.target := Mux(isMret, mepc, mtvec)
 
   when (io.redirect.valid && !isMret) {