- 17 7月, 2021 24 次提交
-
-
由 Lingrui98 提交于
-
由 Lingrui98 提交于
-
由 Lingrui98 提交于
-
由 Lingrui98 提交于
* Now can pass compiling. [WIP] comment out-of-date code in frontend [WIP] move NewFtq to xiangshan.frontend and rename class to Ftq Ibuffer: update sigal names for new IFU [WIP] remove redundant NewFrontend [WIP] set entry_fetch_status to f_sent once send req to buf Fix syntax error in IFU Fix syntax error in IFU/ICache/Ibuffer [WIP] indent fix in ftq BPU: Move GlobalHistory define from IFU.scala to BPU.scala [WIP] fix some compilation errors BPU: Remove HasIFUConst and move some bundles from BPU.scala to frontendBundle.scala [WIP] fix some compilation errors [WIP] rename ftq-bpu ios [WIP] recover some const definitions [WIP] fix some compilation errors [WIP]connect some IOs in frontend BPU: fix syntax error [WIP] fix compilation errors in predecode BPU: fix RAS syntax error [WIP] add some simulation perf counters back BPU: Remove numBr redefine in ubtb and bim
-
由 Lingrui98 提交于
-
由 Lemover 提交于
* CSR: add csr access check for mstatus.tvm tvm: trap virtual Memory. when tvm is set, r/w the satp in S-mode will raise illegal-instr * Fence: add tvm check that may disallow sfence when tvm is set and at s-mode, sfence.vma will raise illegal-instr
-
由 Yinan Xu 提交于
* change the number of function units in MinimalConfig * remove some hard-wired values
-
由 Yinan Xu 提交于
This commit adds support for a parameterized scheduler. A scheduler can be parameterized via issue and dispatch ports. Note: other parameters have not been tested.
-
由 Yinan Xu 提交于
This commit adds an non-parameterized scheduler containing all reservation stations. Now IntegerBlock, FloatBlock, MemBlock contain only function units. The Schduler connects dispatch with all function units. Parameterization to be added later.
-
由 Jiawei Lin 提交于
-
由 Lemover 提交于
* PTW: Repeater support multi req by RRArbiter * ptw: add parameter to choose repeater and filter(default) simple ci test show that: the filter is critical for perf like mcf(5m): old ptw:2.38 new ptw with repeater: 2.41 new ptw with filter: 2.58
-
由 Yinan Xu 提交于
* better select policy timing * unified RS enqueue ports for 4 ALUs * wrap imm extractor into a module * backend,rs: wrap dataArray in RawDataModuleTemplate * should only bypass data between the same addr when allocate.valid
-
由 Lingrui98 提交于
-
由 wakafa 提交于
-
由 Yinan Xu 提交于
-
由 Yinan Xu 提交于
-
由 JinYue 提交于
-
由 JinYue 提交于
* The instruction behind the taken one should be invalid
-
由 Lingrui98 提交于
-
由 Lingrui98 提交于
1. do not allow request enter ifu_req_buf while getting flush from ifu 2. code clean ups
-
由 JinYue 提交于
-
由 JinYue 提交于
-
由 Lingrui98 提交于
-
由 JinYue 提交于
* flush must wait for the state machine say that instructions are valid
-
- 16 7月, 2021 16 次提交
-
-
由 Lingrui98 提交于
-
由 JinYue 提交于
* PreDecode out has no valid
-
由 Lingrui98 提交于
ftq: 1. fix a bug when an entry dequeue too soon 2. add some basic debug info
-
由 Lingrui98 提交于
-
由 JinYue 提交于
-
由 JinYue 提交于
-
由 JinYue 提交于
-
由 Lingrui98 提交于
-
由 Lingrui98 提交于
-
由 zoujr 提交于
-
由 JinYue 提交于
-
由 zoujr 提交于
-
由 zoujr 提交于
-
由 Lingrui98 提交于
-
由 zoujr 提交于
-
由 zoujr 提交于
-