[WIP] finish ftq logic and fix syntax errors

* Now can pass compiling.

[WIP] comment out-of-date code in frontend

[WIP] move NewFtq to xiangshan.frontend and rename class to Ftq

Ibuffer: update sigal names for new IFU

[WIP] remove redundant NewFrontend

[WIP] set entry_fetch_status to f_sent once send req to buf

Fix syntax error in IFU

Fix syntax error in IFU/ICache/Ibuffer

[WIP] indent fix in ftq

BPU: Move GlobalHistory define from IFU.scala to BPU.scala

[WIP] fix some compilation errors

BPU: Remove HasIFUConst
and move some bundles from BPU.scala to frontendBundle.scala

[WIP] fix some compilation errors

[WIP] rename ftq-bpu ios

[WIP] recover some const definitions

[WIP] fix some compilation errors

[WIP]connect some IOs in frontend

BPU: fix syntax error

[WIP] fix compilation errors in predecode

BPU: fix RAS syntax error

[WIP] add some simulation perf counters back

BPU: Remove numBr redefine in ubtb and bim

src/main/scala/xiangshan/Bundle.scala

@@ -30,10 +30,7 @@ import xiangshan.frontend.RASEntry
 import xiangshan.frontend.BPUCtrl
 import xiangshan.frontend.FtqPtr
 import xiangshan.frontend.FtqRead
-<<<<<<< HEAD
 import xiangshan.frontend.FtqToCtrlIO
-=======
->>>>>>> 18cabc2c (core: move ftq to frontend)
 import utils._
 
 import scala.math.max

src/main/scala/xiangshan/XSCore.scala

@@ -21,7 +21,9 @@ import xiangshan.backend._
 import xiangshan.backend.fu.HasExceptionNO
 import xiangshan.backend.exu.Wb
 import xiangshan.frontend._
-import xiangshan.cache.{L1plusCacheWrapper, PTWWrapper, PTWRepeater, PTWFilter}
+import xiangshan.mem._
+import xiangshan.cache.{DCacheParameters, L1plusCacheWrapper, L1plusCacheParameters, PTWWrapper, PTWRepeater, PTWFilter}
+import xiangshan.cache.prefetch._
 import chipsalliance.rocketchip.config
 import chipsalliance.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -183,7 +183,7 @@ class RedirectGenerator(implicit p: Parameters) extends XSModule
 class CtrlBlock(implicit p: Parameters) extends XSModule
   with HasCircularQueuePtrHelper {
   val io = IO(new Bundle {
-    val frontend = Flipped(new FrontendToBackendIO)
+    val frontend = Flipped(new FrontendToCtrlIO)
     val enqIQ = Vec(exuParameters.CriticalExuCnt, DecoupledIO(new MicroOp))
     // from int block
     val exuRedirect = Vec(exuParameters.AluCnt + exuParameters.JmpCnt, Flipped(ValidIO(new ExuOutput)))
@@ -244,7 +244,7 @@ class CtrlBlock(implicit p: Parameters) extends XSModule
   })
   val loadReplay = Wire(Valid(new Redirect))
   loadReplay.valid := RegNext(io.memoryViolation.valid &&
-    !io.memoryViolation.bits.roqIdx.needFlush(backendRedirect, flushReg),
+    !io.memoryViolation.bits.roqIdx.needFlush(stage2Redirect, flushReg),
     init = false.B
   )
   loadReplay.bits := RegEnable(io.memoryViolation.bits, io.memoryViolation.valid)
@@ -350,7 +350,7 @@ class CtrlBlock(implicit p: Parameters) extends XSModule
   }
 
   // TODO: is 'backendRedirect' necesscary?
-  io.redirect <> backendRedirect
+  io.redirect <> stage2Redirect
   io.flush <> flushReg
   io.debug_int_rat <> rename.io.debug_int_rat
   io.debug_fp_rat <> rename.io.debug_fp_rat

src/main/scala/xiangshan/decoupled-frontend/Frontend.scala

@@ -118,18 +118,6 @@ class FrontendImp (outer: Frontend) extends LazyModuleImp(outer)
   io.backend.fromFtq <> ftq.io.toBackend
   io.frontendInfo.bpuInfo <> ftq.io.bpuInfo
 
-  ftq.io.enq <> ifu.io.toFtq
-  ftq.io.roq_commits <> io.backend.toFtq.roq_commits
-  ftq.io.redirect <> io.backend.toFtq.redirect
-  ftq.io.flush := io.backend.toFtq.flush
-  ftq.io.flushIdx := io.backend.toFtq.flushIdx
-  ftq.io.flushOffset := io.backend.toFtq.flushOffset
-  ftq.io.frontendRedirect <> io.backend.toFtq.frontendRedirect
-  ftq.io.exuWriteback <> io.backend.toFtq.exuWriteback
-  io.backend.fromFtq.ftqRead <> ftq.io.ftqRead
-  io.backend.fromFtq.cfiRead <> ftq.io.cfiRead
-  io.frontendInfo.bpuInfo <> ftq.io.bpuInfo
-
 
   instrUncache.io.req   <> DontCare
   instrUncache.io.resp  <> DontCare

src/main/scala/xiangshan/decoupled-frontend/ICache.scala

@@ -228,7 +228,7 @@ class ICacheDataArray(implicit p: Parameters) extends ICacheArray
 
   (io.readResp.datas zip dataArrays).map {case (io, sram) => io :=  VecInit(sram.map(way => way.io.r.resp.data.asTypeOf(UInt(blockBits.W)) ))  }
 
-  io.write.ready := DontCare
+  io.write.ready := true.B
 }
 
 

src/main/scala/xiangshan/decoupled-frontend/IFU.scala

@@ -16,7 +16,11 @@ trait HasInstrMMIOConst extends HasXSParameter with HasIFUConst{
 }
 
 trait HasIFUConst extends HasXSParameter {
+<<<<<<< HEAD
   val resetVector = 0x80000000L//TODO: set reset vec
+=======
+  val resetVector = 0x10000000L//TODO: set reset vec
+>>>>>>> 06cc0051 ([WIP] finish ftq logic and fix syntax errors)
   def align(pc: UInt, bytes: Int): UInt = Cat(pc(VAddrBits-1, log2Ceil(bytes)), 0.U(log2Ceil(bytes).W))
   val groupBytes = 64 // correspond to cache line size
   val groupOffsetBits = log2Ceil(groupBytes)
@@ -319,8 +323,12 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
   io.toIbuffer.bits.valid     := f2_real_valids
   io.toIbuffer.bits.pd        := preDecoderOut.pd
   io.toIbuffer.bits.ftqPtr    := f2_ftq_req.ftqIdx
+<<<<<<< HEAD
   io.toIbuffer.bits.pc        := preDecoderOut.pc
   io.toIbuffer.bits.ftqOffset.zipWithIndex.map{case(a, i) => a.bits := i.U; a.valid := preDecoderOut.takens(i)}
+=======
+  io.toIbuffer.bits.ftqOffset := preDecoderOut.pc
+>>>>>>> 06cc0051 ([WIP] finish ftq logic and fix syntax errors)
   io.toIbuffer.bits.foldpc    := preDecoderOut.pc.map(i => XORFold(i(VAddrBits-1,1), MemPredPCWidth))
 
 

src/main/scala/xiangshan/decoupled-frontend/NewFtq.scala

@@ -174,6 +174,9 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   val backendFlush = stage2Flush || RegNext(stage2Flush)
   val ifuFlush = io.fromIfu.pdWb.valid && io.fromIfu.pdWb.bits.misOffset.valid
 
+  val stage2Flush = io.fromBackend.stage2Redirect.valid || io.fromBackend.roqFlush.valid
+  val flush = stage2Flush || RegNext(stage2Flush)
+  
   val bpuPtr, ifuPtr, commPtr = RegInit(FtqPtr(false.B, 0.U))
   val validEntries = distanceBetween(bpuPtr, commPtr)