* ctrl: copy dispatch2 to avoid cross-module loops

This commit makes copies of dispatch2 in CtrlBlock to avoid long
cross-module timing loop paths. Should be good for timing.

* dpq: re-write queue read logic

This commit adds a Reg-Vec to store the queue read data. Since
most queues read at most the current numRead and the next numRead
entries, the read timing can be optimized by reading the data one
cycle earlier.

This commit optimizes the timing of reservation stations.

* dispatched uops are latched and bypassed to s1_out

* wakeup from slowPorts are latched and bypassed to s1_data

* rs: optimize allocation selection

Change select policy for allocation. Should avoid issuing the just
dispatched instructions in some cases.

* rs: disable load balance for load units

The VGA device may cause assertions in AXI4SlaveModule because it
may send arbitrary requests to fb (AXI4RAM).

This commit fixes the bug that instructions with exceptions may trigger
instruction fusion if the previous instruction at the same position is
fused. When the input instruction pair is invalid, the fusion decoder
should always set out.valid to false.B at the next cycle.

The bug is caused by the RegEnable for instrPairValid, which should be
updated at every clock cycle.

Should fix the error introduced by 0febc381
and the regression failure at https://github.com/OpenXiangShan/XiangShan/actions/runs/2645135867.

dcache: optimize timing for probe req entering main pipe

MissQueue: use FastArbiter for replace req

This commit adds separated redirect registers in ExuBlock and MemBlock.
They have one cycle latency compared to redirect in CtrlBlock. This will
help reduce the fanout of redirect registers.

This commit moves the fusion decoder to both decode and rename stage.

In the decode stage, fusion decoder determines whether the instruction
pairs can be fused. Valid bits of decode are not affected by fusion
decoder. This should fix the timing issues of rename.valid.

In the rename stage, some fields are updated according the result of
fusion decoder. This will bring a minor timing path to both valid and
other fields in uop in the rename stage. However, since freelist and
rat have worse timing. This should not cause timing issues.

* dtlb: replace sram to SyncDataModule, nWays is useless

* itlb: if miss_sameCycle, regnext ptw resp and block tlb check

* dtlb: for normal_entry, when refill, do not need set miss by force

* Update build.sc

* Update build.sc

This commit fixes the bug that the lsrc(0) of trap instructions is
overrided with $a0, which causes timing issues as well.

This commit adds a pipeline for performance counters. No functional changes.

* Remove unused field isRVF
* Replace 3rd srcType of non-fp insts and FuType.{fmisc, i2f} insts with SrcType.X

Some modules rely on the walk valid bits of ROB. This commit
optimizes the timing by providing separated walk valid bits, which
is far better than the commit valid bits.

This commit changes the data modules in Dispatch Queue. We use one-hot
indices to read and write the data array.

Optimize the naive implementation of performance counters in decode.

timing optimizations for bpu and ftq

* add one cycle stall to ftb miss update, and
* add one cycle delay to all other predictors

ftq: add one cycle delay to write status registers, and add more bypass logic for entry_fetch_status

This commit re-pipelines ECC check logic in data cache and exception generate logic for better timing.
Now ecc error is checked 1 cycle after reading result from data sram. An extra cycle is added for load
writeback to ROB.

Future work: move the pipeline to https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/backend/CtrlBlock.scala#L266-L277, which add a regnext.

* dcache: repipeline ecc check logic for timing

* chore: fix normal loadAccessFault logic

* wbu: delay load unit wb for 1 cycle

* dcache: add 1 extra cycle for beu error report

* dp2: add a pipeline for load/store

Load/store Dispatch2 has a bad timing because it requires the fuType
to disguish the out ports. This brings timing issues because the
instruction has to read busyTable after the port arbitration.

This commit adds a pipeline in dp2Ls, which may cause performance
degradation. Instructions are dispatched according to out, and at
the next cycle it will leave dp2.

* bump difftest trying to fix vcs

* dcache: do not access plru when refill

Now we have accessed plru when load miss, we should not access plru
when refill

* dcache: not not access plru when miss queue full

It will help avoid invalid plru access when miss queue full

fix some bugs.

1. fix l2tlb dead-lock bug
l2tlb won't merge requests at same addr. It will be blocked when having too many requests.
PtwFilter has a bug that will send too many requests. Add a counter to avoid that.

2. fix sfence sync at mmu
different modules in mmu may get sfence at different latency, which will lost requests or some requests have no receiver.
Sync the sfence latency manually to avoid the bug.

* mmu.filter: add counter not to send to many req to l2tlb

* mmu.filter: fix bug that forget counter signal when block issue and deq

* mmu: set sfence/csr delay to 2 cycle, must sync in mmu

now the l2tlb page cache are divided into:
1. stageReq: input && read sram valid && will block when sram write
2. stageDelay: get sram data and delay one cycle
3. stageCheck: check hit and ecc result
4. stageResp: output

Background:
dtlb has 128 entries stored in sram. 128 sets, 1 ways.
advantage: large volume & 1 ways means no tag match logic at data select path
disadvantage: 128 sets means long latency at valid select, which is a Vec-Register.

Optimization: divide valid select into two-cycles

This commit optimizes the timing of freelist by changing the updating
function of headPtr and tailPtr.

We maintains an one-hot representation of headPtr and further uses it to
read the free registers from the list, which should be better than the
previous implementation where headPtr is used to indexed into the queue.

The update of tailPtr and the freelist is delayed by one cycle to
optimize the timing. Because freelist allocates new registers in the
next cycle iff there are more than RenameWidth free registers in this
cycle. The freed registers in this cycle will never be used in the next
cycle. Thus, we can delay the updating of queue data to the next cycle.
We also move the update of tailPtr to the next cycle, since PopCount
takes a long timing and we move the last adder to the next cycle. Now
the adder works parallely with PopCount. That is, the updating of
tailPtr is pipelined.

Added chisel-db to dump hw data into a database automatically

This commit adds a buffer after the function unit that operate across
the integer block and the floating-point block, such as f2i and i2f.

For example, previously the out.ready of f2i depends on whether
mul/div/csr/jump has a valid instruction out, since f2i has lower
priority than them. This ready back-propagates from the integer function
units to the floating-point function units, and finally to the
floating-point reservation stations (since f2i is fully pipelined).

We add a buffer after the function unit to break this ready
back-propagation. It incurs one more cycle of execution latency, but we
leave it not-fully-optimized for now.

Timing can be further optimized if we separates the int writeback and fp
writeback in function units. In the current version, the ready of f2i
affects the ready of f2f pipelines, which is unnecessary. This is the
future work.

This commit adds some registers for performance counters to optimize
the timing. Pipelines are added.

This commit changes the lsrc/psrc of LUI in dispatch instead of
decode to optimize the timing of lsrc in DecodeStage, which is
critical for rename table.

lsrc/ldest should be directly get from instr for the timing. Fused
instructions change lsrc/ldest now, which will be optimized later.

* buspmu: avoid inner space in perf-cnt name

* perfcnt: judge regularity of perfname

* perfcnt: fix some irregular perfname

* bump huancun