When sbuffer checks if it is empty, it needs to check if sq is also empty
so there is no pending store. Errors will emerge rarely if we do not
check sq.

* Gen selectMask in 2nd cycle, in parallel with DeqMask

We used to select writeback inst and update writebacked bit
at the same cycle. However, it is too long to finish in one cycle.

Now we select writeback inst and gen wbSelectedMask in cycle 1,
then we use RegNext(wbSelectedMask) and writeback bit to select
inst in the next cycle.

* values of hardware performance counters can hardly be emulated by NEMU

Now we have:
* paddrModule
* maskModule
* exceptionModule
* coredataModule (data & fwdmask)

This reverts commit 2e0406ca.

* Stage 0
* Generate writeback indexes
* Mark them as writebacked so they will not be selected the next cycle

Stage 1
* Use indexes generated in cycle 0 to read data
* Writeback data to cdb

Now storequeue dataModule is divided into 3 modules:
* vaddrModule (2w1r)
* exceptionModule (2w1r)
* dataModule (core data module, 2w2r+fwd)

Fp load uses different wb port from int load for 2 reasons:
* Fp load needs recode, which is quite slow. We need one complete cycle
for recoding.
* Fp load data has nothing to do with int load data. There is no reason
to mix them together.

An extra recode stage (load_s3) is added for fp load, while int load will
still be writebackd at load_s2.