* test: add example to genenrate verilog for a small module

Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop

* test: add DecodeUnitTest as an example for xs' chiseltest

* ctrlblock: <> usage has changed, unidirection should use :=

* bump huancun

* makefile: mv new makefile cmd into Makefile.test

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

* add 1 stage for mmio_state before sending request to MMIO bus
* check whether the last fetch packet commit all its intructions (the
result of execution path has been decided)
* avoid speculative execution to MMIO bus

Previously the BranchPredictionUpdate bundle was inherited from
BranchPredictionBundle, and that made some field of the bundle
unused. It was hard to find which signals are really in use.
Now we make BranchPredictionUpdate a independent bundle, so that
the signals in it are all in use.

* copy Ftq to ICache read valid signal

* move sram read data and miss data selection to IFU (after predecode)

* copy address select signal for every copied port
* add 1 more copy for itlb request use
* add 1 cycle latency for ftq_pc_mem read before sending to IPrefetch

* should use RegNext on ftq_pc_mem rdata with the wrapper implementation now

ftq, ctrl: fix newest_target logic, pass it to ctrlblock, remove jalrTargetMem and read target from pc_mem

* add diff for upate_target and pc_mem result

ftq, ctrl: add second write port logic of jalrTargetMem, and delay write of pc/target mem for two cycles

* FtqToICache add bypass write signal and use bypass signal

* IFU: ignore ICache access bundle

* ICacheMainPipe: expand meta/data access output to 4 identical vector
output, each output is connected to a copied register trigger by FTQ
requests

* IPrefetch/ReplacePipe: expand meta/data access outpu to 4 indentical
vector output, and each output is triggered by the same signal group

* separate ifu req and icache req for timing optimization

* both ifu ftq_req_ready and icache ftq_req_ready depend on each other

* ifu and icache has pc_mem register

[WIP]ICacheMainPipe: add copied registers

[WIP]ftq: read ftq_pc_mem one cycle ahead, reqs to be copied

[WIP] FTQ:  delete outside bypass

* ftq, ctrl: remove pc/target backend read ports, and remove redirectGen in ftq

* ctrl: add data modules for pc and jalr_target

This commit adds two data modules for pc and jalr_target respectively.
They are the same as data modules in frontend. Should benefit timing.

* jump: reduce pc and jalr_target read latency

* ftq: add predecode redirect update target interface, valid only on ifuRedirect

* ftq, ctrl: add second write port logic of jalrTargetMem, and delay write of pc/target mem for two cycles
Co-authored-by: NLingrui98 <goulingrui19s@ict.ac.cn>

and remove all bypass for ftq_pc_mem

  IFU: Add toIBuffer and toFtq record
  Ftq: Add branch trace datebase framework

* ftq, ctrl: remove pc/target backend read ports, and remove redirectGen in ftq

* ctrl: add data modules for pc and jalr_target

This commit adds two data modules for pc and jalr_target respectively.
They are the same as data modules in frontend. Should benefit timing.

* jump: reduce pc and jalr_target read latency

* ftq: add predecode redirect update target interface, valid only on ifuRedirect

* ftq, ctrl: add second write port logic of jalrTargetMem, and delay write of pc/target mem for two cycles
Co-authored-by: NLingrui98 <goulingrui19s@ict.ac.cn>

* add one cycle stall to ftb miss update, and
* add one cycle delay to all other predictors