* test: add example to genenrate verilog for a small module

Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop

* test: add DecodeUnitTest as an example for xs' chiseltest

* ctrlblock: <> usage has changed, unidirection should use :=

* bump huancun

* makefile: mv new makefile cmd into Makefile.test

Here is a bug cause by EnableUncacheWriteOutstanding:
The case is extintr in Nexus-AM.
Three steps of the test:
  clear intrGen's intr: Stop pass interrupt. A mmio write.
  clear plic claim: complete intr. A mmio write.
  read plic claim to check: claim should be 0. A mmio read.
The corner case:
  intrGen's mmio write is to slow. The instruction after it executes
and plic claim's mmio's write & read execute before it. On the side of
core with plic, claim is cleared. But on the side of intrGen with plic,
the source of interrupt is still enabled and trigger interrupt.
So the "read plic claim to check" get a valid claim and failed.

Software prefetch flow (from storeprefetch uop) will not be replayed
unless tlb reports a miss. In that case, software prefetch flow behaves
like an normal tlb missed load.

Hardware prefetch flow will never be replayed.

This commit refactors ldu load_s0 load flow arbitor logic.

Now there are 6 load flow sources, which are (priority high -> low):

src0: load replayed by LSQ (io.lsqOut)
src1: hardware prefetch from prefetchor (high confidence) (io.prefetch)
src2: int read / software prefetch first issue from RS (io.in)
src3: vec read first issue from RS (TODO)
src4: load try pointchaising when no issued or replayed load (io.fastpath)
src5: hardware prefetch from prefetchor (high confidence) (io.prefetch)

Co-authored-by: NZhangZifei <1773908404@qq.com>

TODO: ldflow from prefetch to be added to ldflow select logic

Now SMS is the same as f684ed00

TLB and Huancun conflict fix is not included in this commit

This commit update coh check assertion to enable aggressive
prefetch miss req / store miss req merge. Previous wrong
assertion forbids store req from stoping a previous prefetch

For example, consider 2 reqs with the same p address fire in order:
1) A prefetch with alias bit 00 need to change coh state from N->T
2) A store with alias bit 11 need to change coh state from B->T
Then prefetch and store miss req will be merged in the same missq
entry. Store req (2) should be able to stop prefetch (1) so that a
ping-pong process will not start

Note that Huancun have not been updated in this commit

No extra latency introduced

Added meta_prefetch and meta_access related sim perf counter

For now, optional dcache meta prefetch and access can be removed safely