BOP: support only prefetch store

src/main/scala/xiangshan/Bundle.scala

@@ -483,6 +483,7 @@ class CustomCSRCtrlIO(implicit p: Parameters) extends XSBundle {
   val l1D_pf_enable_pht = Output(Bool())
   val l1D_pf_active_threshold = Output(UInt(4.W))
   val l1D_pf_active_stride = Output(UInt(6.W))
+  val l2_pf_store_only = Output(Bool())
   // ICache
   val icache_parity_enable = Output(Bool())
   // Labeled XiangShan

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -127,6 +127,7 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
 
   val csrCtrl = DelayN(io.csrCtrl, 2)
   dcache.io.csr.distribute_csr <> csrCtrl.distribute_csr
+  dcache.io.l2_pf_store_only := RegNext(io.csrCtrl.l2_pf_store_only, false.B)
   io.csrUpdate := RegNext(dcache.io.csr.update)
   io.error <> RegNext(RegNext(dcache.io.error))
   when(!csrCtrl.cache_error_enable){

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -491,14 +491,15 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
   // spfctl Bit [15:10]: L1D prefetch active page stride
   // turn off L2 BOP, turn on L1 SMS by default
   val spfctl = RegInit(UInt(XLEN.W), Seq(
-    30 << 10,    // L1D active page stride [15:10]
-    12 << 6,    // L1D active page threshold [9:6]
-    0  << 5,    // L1D enable pht [5]
-    1  << 4,    // L1D enable agt [4]
-    0  << 3,    // L1D train on hit agt [3]
-    1  << 2,    // L1D pf enable [2]
-    0  << 1,    // L2 pf enable [1]
-    1  << 0,    // L1I pf enable [0]
+    0 << 16,    // L2 pf store only [16] init: false
+    30 << 10,   // L1D active page stride [15:10] init: 30
+    12 << 6,    // L1D active page threshold [9:6] init: 12
+    1  << 5,    // L1D enable pht [5] init: true
+    1  << 4,    // L1D enable agt [4] init: true
+    0  << 3,    // L1D train on hit [3] init: false
+    1  << 2,    // L1D pf enable [2] init: true
+    1  << 1,    // L2 pf enable [1] init: true
+    1  << 0,    // L1I pf enable [0] init: true
   ).reduce(_|_).U(XLEN.W))
   csrio.customCtrl.l1I_pf_enable := spfctl(0)
   csrio.customCtrl.l2_pf_enable := spfctl(1)
@@ -508,6 +509,7 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
   csrio.customCtrl.l1D_pf_enable_pht := spfctl(5)
   csrio.customCtrl.l1D_pf_active_threshold := spfctl(9, 6)
   csrio.customCtrl.l1D_pf_active_stride := spfctl(15, 10)
+  csrio.customCtrl.l2_pf_store_only := spfctl(16)
 
   // sfetchctl Bit 0: L1I Cache Parity check enable
   val sfetchctl = RegInit(UInt(XLEN.W), "b0".U)

src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala

@@ -646,6 +646,7 @@ class DCacheToLsuIO(implicit p: Parameters) extends DCacheBundle {
 
 class DCacheIO(implicit p: Parameters) extends DCacheBundle {
   val hartId = Input(UInt(8.W))
+  val l2_pf_store_only = Input(Bool())
   val lsu = new DCacheToLsuIO
   val csr = new L1CacheToCsrIO
   val error = new L1CacheErrorInfo
@@ -710,6 +711,7 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
   val wb         = Module(new WritebackQueue(edge))
 
   missQueue.io.hartId := io.hartId
+  missQueue.io.l2_pf_store_only := RegNext(io.l2_pf_store_only, false.B)
 
   val errors = ldu.map(_.io.error) ++ // load error
     Seq(mainPipe.io.error) // store / misc error 

src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala

@@ -167,6 +167,7 @@ class MissEntry(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule {
     val req_handled_by_this_entry = Output(Bool())
 
     val forwardInfo = Output(new MissEntryForwardIO)
+    val l2_pf_store_only = Input(Bool())
   })
 
   assert(!RegNext(io.primary_valid && !io.primary_ready))
@@ -611,6 +612,7 @@ class MissQueue(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule wi
 
     // forward missqueue
     val forward = Vec(LoadPipelineWidth, new LduToMissqueueForwardIO)
+    val l2_pf_store_only = Input(Bool())
   })
   
   // 128KBL1: FIXME: provide vaddr for l2
@@ -677,6 +679,7 @@ class MissQueue(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule wi
       
       e.io.hartId := io.hartId
       e.io.id := i.U
+      e.io.l2_pf_store_only := io.l2_pf_store_only
       e.io.req.valid := io.req.valid
       e.io.primary_valid := io.req.valid && 
         !merge &&