* core: enable sc

* sc: calculate sum again on update

* sc: clean ups

* sc: add some debug info

* sc, tage, bim: fix wrbypass logic, add wrbypass for SC

* sc: restrict threshold update conditions and prevent overflow problem

* sc: use seperative thresholds for each bank

* sc: update debug info

* sc: use adaptive threshold algorithm from the original O-GEHL

* tage, bim, sc: optimize wrbypass logic

* sc: initialize threshold to 60

* loop: remove unuseful RegNext on redirect

* Replacement: change state in way method.

* State change is also needed when miss occurs, otherwise we will choose
a way that has been just refilled into cache as the victim.

* Optimize ctrlblock timing (#620)

* CtrlBlock: delay exception flush for 1 cycle

* CtrlBlock: delay load replay for 1 cycle

* roq: delay wb from exu for one clock cycle to meet timing

* CtrlBlock: fix pipeline bug between decode and rename
Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>

* L1plusCache: use plru replacement policy.

* ICache: fix mmio bugs

1. MMIO cut helper uses packet align logic
2. still send req to uncache when flush

* ICache: change packet from mmio

use packet align as the mem

* IntrUncache: fix state bug

state will change into s_invalid and get stuck

* fix Registers that not being initiated

* core: enable sc

* sc: calculate sum again on update

* sc: clean ups

* sc: add some debug info

* sc, tage, bim: fix wrbypass logic, add wrbypass for SC

* core: disable sc by default
Co-authored-by: Njinyue110 <jinyue161@mails.ucas.ac.cn>

* csr: add sbpctrl to control branch predictors

* bpu: add dynamic switch to each predictor

* csr: change spfctl and sbpctl address

* bpu: fix s3 connections
Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>

     for bim, btb, tage and ubtb