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26549752
编写于
2月 17, 2021
作者:
L
Lingrui98
浏览文件
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电子邮件补丁
差异文件
sram template: support multi-way write
上级
70e9016b
变更
8
隐藏空白更改
内联
并排
Showing
8 changed file
with
23 addition
and
15 deletion
+23
-15
src/main/scala/utils/SRAMTemplate.scala
src/main/scala/utils/SRAMTemplate.scala
+13
-5
src/main/scala/xiangshan/backend/ftq/Ftq.scala
src/main/scala/xiangshan/backend/ftq/Ftq.scala
+1
-1
src/main/scala/xiangshan/cache/ICache.scala
src/main/scala/xiangshan/cache/ICache.scala
+1
-1
src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala
...n/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala
+2
-2
src/main/scala/xiangshan/frontend/Bim.scala
src/main/scala/xiangshan/frontend/Bim.scala
+1
-1
src/main/scala/xiangshan/frontend/Btb.scala
src/main/scala/xiangshan/frontend/Btb.scala
+3
-3
src/main/scala/xiangshan/frontend/SC.scala
src/main/scala/xiangshan/frontend/SC.scala
+1
-1
src/main/scala/xiangshan/frontend/Tage.scala
src/main/scala/xiangshan/frontend/Tage.scala
+1
-1
未找到文件。
src/main/scala/utils/SRAMTemplate.scala
浏览文件 @
26549752
...
...
@@ -29,15 +29,20 @@ class SRAMBundleA(val set: Int) extends Bundle {
}
class
SRAMBundleAW
[
T
<:
Data
](
private
val
gen
:
T
,
set
:
Int
,
val
way
:
Int
=
1
)
extends
SRAMBundleA
(
set
)
{
val
data
=
Output
(
gen
)
val
data
=
Output
(
Vec
(
way
,
gen
)
)
val
waymask
=
if
(
way
>
1
)
Some
(
Output
(
UInt
(
way
.
W
)))
else
None
def
apply
(
data
:
T
,
setIdx
:
UInt
,
waymask
:
UInt
)
=
{
def
apply
(
data
:
Vec
[
T
],
setIdx
:
UInt
,
waymask
:
UInt
)
:
SRAMBundleAW
[
T
]
=
{
super
.
apply
(
setIdx
)
this
.
data
:=
data
this
.
waymask
.
map
(
_
:=
waymask
)
this
}
// this could only be used when waymask is onehot or nway is 1
def
apply
(
data
:
T
,
setIdx
:
UInt
,
waymask
:
UInt
)
:
SRAMBundleAW
[
T
]
=
{
apply
(
VecInit
(
Seq
.
fill
(
way
)(
data
)),
setIdx
,
waymask
)
this
}
}
class
SRAMBundleR
[
T
<:
Data
](
private
val
gen
:
T
,
val
way
:
Int
=
1
)
extends
Bundle
{
...
...
@@ -58,11 +63,15 @@ class SRAMReadBus[T <: Data](private val gen: T, val set: Int, val way: Int = 1)
class
SRAMWriteBus
[
T
<:
Data
](
private
val
gen
:
T
,
val
set
:
Int
,
val
way
:
Int
=
1
)
extends
Bundle
{
val
req
=
Decoupled
(
new
SRAMBundleAW
(
gen
,
set
,
way
))
def
apply
(
valid
:
Bool
,
data
:
T
,
setIdx
:
UInt
,
waymask
:
UInt
)
=
{
def
apply
(
valid
:
Bool
,
data
:
Vec
[
T
],
setIdx
:
UInt
,
waymask
:
UInt
)
:
SRAMWriteBus
[
T
]
=
{
this
.
req
.
bits
.
apply
(
data
=
data
,
setIdx
=
setIdx
,
waymask
=
waymask
)
this
.
req
.
valid
:=
valid
this
}
def
apply
(
valid
:
Bool
,
data
:
T
,
setIdx
:
UInt
,
waymask
:
UInt
)
:
SRAMWriteBus
[
T
]
=
{
apply
(
valid
,
VecInit
(
Seq
.
fill
(
way
)(
data
)),
setIdx
,
waymask
)
this
}
}
class
SRAMTemplate
[
T
<:
Data
](
gen
:
T
,
set
:
Int
,
way
:
Int
=
1
,
...
...
@@ -89,9 +98,8 @@ class SRAMTemplate[T <: Data](gen: T, set: Int, way: Int = 1,
val
realRen
=
(
if
(
singlePort
)
ren
&&
!
wen
else
ren
)
val
setIdx
=
Mux
(
resetState
,
resetSet
,
io
.
w
.
req
.
bits
.
setIdx
)
val
wdata
word
=
Mux
(
resetState
,
0.
U
.
asTypeOf
(
wordType
),
io
.
w
.
req
.
bits
.
data
.
asUInt
)
val
wdata
=
VecInit
(
Mux
(
resetState
,
0.
U
.
asTypeOf
(
Vec
(
way
,
gen
)),
io
.
w
.
req
.
bits
.
data
).
map
(
_
.
asTypeOf
(
wordType
))
)
val
waymask
=
Mux
(
resetState
,
Fill
(
way
,
"b1"
.
U
),
io
.
w
.
req
.
bits
.
waymask
.
getOrElse
(
"b1"
.
U
))
val
wdata
=
VecInit
(
Seq
.
fill
(
way
)(
wdataword
))
when
(
wen
)
{
array
.
write
(
setIdx
,
wdata
,
waymask
.
asBools
)
}
val
rdata
=
(
if
(
holdRead
)
ReadAndHold
(
array
,
io
.
r
.
req
.
bits
.
setIdx
,
realRen
)
...
...
src/main/scala/xiangshan/backend/ftq/Ftq.scala
浏览文件 @
26549752
...
...
@@ -53,7 +53,7 @@ class FtqNRSRAM[T <: Data](gen: T, numRead: Int) extends XSModule {
io
.
rdata
(
i
)
:=
sram
.
io
.
r
.
resp
.
data
(
0
)
sram
.
io
.
w
.
req
.
valid
:=
io
.
wen
sram
.
io
.
w
.
req
.
bits
.
setIdx
:=
io
.
waddr
sram
.
io
.
w
.
req
.
bits
.
data
:=
io
.
wdata
sram
.
io
.
w
.
req
.
bits
.
data
:=
VecInit
(
io
.
wdata
)
}
}
...
...
src/main/scala/xiangshan/cache/ICache.scala
浏览文件 @
26549752
...
...
@@ -261,7 +261,7 @@ class ICacheDataArray extends ICachArray
for
(
b
<-
0
until
nBanks
){
dataArray
(
w
)(
b
).
io
.
w
.
req
.
valid
:=
io
.
write
.
valid
&&
w
.
U
===
write_way
dataArray
(
w
)(
b
).
io
.
w
.
req
.
bits
.
setIdx
:=
write
.
virIdx
dataArray
(
w
)(
b
).
io
.
w
.
req
.
bits
.
data
:=
write_bank_data
(
b
)
dataArray
(
w
)(
b
).
io
.
w
.
req
.
bits
.
data
:=
VecInit
(
write_bank_data
(
b
)
)
}
}
...
...
src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala
浏览文件 @
26549752
...
...
@@ -158,8 +158,8 @@ class RecentRequestTable(p: BOPParameters) extends PrefetchModule {
val
wAddr
=
io
.
w
.
bits
rrTable
.
io
.
w
.
req
.
valid
:=
io
.
w
.
valid
&&
!
io
.
r
.
req
.
valid
rrTable
.
io
.
w
.
req
.
bits
.
setIdx
:=
idx
(
wAddr
)
rrTable
.
io
.
w
.
req
.
bits
.
data
.
valid
:=
true
.
B
rrTable
.
io
.
w
.
req
.
bits
.
data
.
tag
:=
tag
(
wAddr
)
rrTable
.
io
.
w
.
req
.
bits
.
data
(
0
)
.
valid
:=
true
.
B
rrTable
.
io
.
w
.
req
.
bits
.
data
(
0
)
.
tag
:=
tag
(
wAddr
)
val
rAddr
=
io
.
r
.
req
.
bits
.
addr
-
(
io
.
r
.
req
.
bits
.
testOffset
<<
log2Up
(
blockBytes
))
val
rData
=
Wire
(
rrTableEntry
())
...
...
src/main/scala/xiangshan/frontend/Bim.scala
浏览文件 @
26549752
...
...
@@ -105,7 +105,7 @@ class BIM extends BasePredictor with BimParams {
for
(
b
<-
0
until
BimBanks
)
{
bim
(
b
).
io
.
w
.
req
.
valid
:=
needToUpdate
(
b
)
||
doing_reset
bim
(
b
).
io
.
w
.
req
.
bits
.
setIdx
:=
Mux
(
doing_reset
,
resetRow
,
updateRow
)
bim
(
b
).
io
.
w
.
req
.
bits
.
data
:=
Mux
(
doing_reset
,
2.
U
(
2.
W
),
newCtrs
(
b
))
bim
(
b
).
io
.
w
.
req
.
bits
.
data
:=
VecInit
(
Mux
(
doing_reset
,
2.
U
(
2.
W
),
newCtrs
(
b
)
))
}
if
(
BPUDebug
&&
debug
)
{
...
...
src/main/scala/xiangshan/frontend/Btb.scala
浏览文件 @
26549752
...
...
@@ -198,16 +198,16 @@ class BTB extends BasePredictor with BTBParams{
for
(
b
<-
0
until
BtbBanks
)
{
meta
(
w
)(
b
).
io
.
w
.
req
.
valid
:=
updateValid
&&
b
.
U
===
updateBank
&&
w
.
U
===
updateWay
meta
(
w
)(
b
).
io
.
w
.
req
.
bits
.
setIdx
:=
updateRow
meta
(
w
)(
b
).
io
.
w
.
req
.
bits
.
data
:=
metaWrite
meta
(
w
)(
b
).
io
.
w
.
req
.
bits
.
data
:=
VecInit
(
metaWrite
)
data
(
w
)(
b
).
io
.
w
.
req
.
valid
:=
updateValid
&&
b
.
U
===
updateBank
&&
w
.
U
===
updateWay
data
(
w
)(
b
).
io
.
w
.
req
.
bits
.
setIdx
:=
updateRow
data
(
w
)(
b
).
io
.
w
.
req
.
bits
.
data
:=
dataWrite
data
(
w
)(
b
).
io
.
w
.
req
.
bits
.
data
:=
VecInit
(
dataWrite
)
}
}
edata
.
io
.
w
.
req
.
valid
:=
updateValid
&&
new_extended
edata
.
io
.
w
.
req
.
bits
.
setIdx
:=
updateRow
edata
.
io
.
w
.
req
.
bits
.
data
:=
u
.
target
edata
.
io
.
w
.
req
.
bits
.
data
:=
VecInit
(
u
.
target
)
if
(
BPUDebug
&&
debug
)
{
...
...
src/main/scala/xiangshan/frontend/SC.scala
浏览文件 @
26549752
...
...
@@ -96,7 +96,7 @@ class SCTable(val nRows: Int, val ctrBits: Int, val histLen: Int) extends BaseSC
table
(
b
)(
i
).
io
.
w
.
req
.
valid
:=
(
io
.
update
.
mask
(
b
)
&&
i
.
U
===
io
.
update
.
tagePred
.
asUInt
)
||
doing_reset
table
(
b
)(
i
).
io
.
w
.
req
.
bits
.
setIdx
:=
Mux
(
doing_reset
,
reset_idx
,
update_idx
)
table
(
b
)(
i
).
io
.
w
.
req
.
bits
.
data
:=
Mux
(
doing_reset
,
0.
S
,
update_wdata
)
table
(
b
)(
i
).
io
.
w
.
req
.
bits
.
data
:=
VecInit
(
Mux
(
doing_reset
,
0.
S
,
update_wdata
)
)
}
}
...
...
src/main/scala/xiangshan/frontend/Tage.scala
浏览文件 @
26549752
...
...
@@ -218,7 +218,7 @@ class TageTable(val nRows: Int, val histLen: Int, val tagLen: Int, val uBitPerio
(
0
until
TageBanks
).
map
(
b
=>
{
table
(
b
).
io
.
w
.
req
.
valid
:=
io
.
update
.
mask
(
b
)
||
doing_reset
table
(
b
).
io
.
w
.
req
.
bits
.
setIdx
:=
Mux
(
doing_reset
,
reset_idx
,
update_idx
)
table
(
b
).
io
.
w
.
req
.
bits
.
data
:=
Mux
(
doing_reset
,
0.
U
.
asTypeOf
(
new
TageEntry
),
update_wdata
(
b
))
table
(
b
).
io
.
w
.
req
.
bits
.
data
:=
VecInit
(
Mux
(
doing_reset
,
0.
U
.
asTypeOf
(
new
TageEntry
),
update_wdata
(
b
)
))
})
val
update_hi_wdata
=
Wire
(
Vec
(
TageBanks
,
Bool
()))
...
...
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