tage: rename more signals

src/main/scala/xiangshan/frontend/Tage.scala

@@ -435,12 +435,12 @@ class Tage extends BaseTage {
   override val debug = true
 
   // Keep the table responses to process in s3
-  val resps = VecInit(tables.map(t => RegEnable(t.io.resp, enable=io.s3Fire)))
-  val scResps = VecInit(scTables.map(t => RegEnable(t.io.resp, enable=io.s3Fire)))
+  val if4_resps = RegEnable(VecInit(tables.map(t => t.io.resp)), enable=io.s3Fire)
+  val if4_scResps = RegEnable(VecInit(scTables.map(t => t.io.resp)), enable=io.s3Fire)
   // val flushLatch = RegNext(io.flush)
 
-  val s2_bim = RegEnable(io.bim, enable=io.pc.valid) // actually it is s2Fire
-  val s3_bim = RegEnable(s2_bim, enable=io.s3Fire)
+  val if3_bim = RegEnable(io.bim, enable=io.pc.valid) // actually it is s2Fire
+  val if4_bim = RegEnable(if3_bim, enable=io.s3Fire)
 
   val debug_pc_s2 = RegEnable(io.pc.bits, enable=io.pc.valid)
   val debug_pc_s3 = RegEnable(debug_pc_s2, enable=io.s3Fire)
@@ -482,37 +482,37 @@ class Tage extends BaseTage {
 
   // access tag tables and output meta info
   for (w <- 0 until TageBanks) {
-    val tageTaken = WireInit(s3_bim.ctrs(w)(1).asBool)
-    var altPred = s3_bim.ctrs(w)(1)
-    val finalAltPred = WireInit(s3_bim.ctrs(w)(1))
-    var provided = false.B
-    var provider = 0.U
-    io.resp.takens(w) := s3_bim.ctrs(w)(1)
+    val if4_tageTaken = WireInit(if4_bim.ctrs(w)(1).asBool)
+    var if4_altPred = if4_bim.ctrs(w)(1)
+    val if4_finalAltPred = WireInit(if4_bim.ctrs(w)(1))
+    var if4_provided = false.B
+    var if4_provider = 0.U
+    io.resp.takens(w) := if4_bim.ctrs(w)(1)
 
     for (i <- 0 until TageNTables) {
-      val hit = resps(i)(w).valid
-      val ctr = resps(i)(w).bits.ctr
+      val hit = if4_resps(i)(w).valid
+      val ctr = if4_resps(i)(w).bits.ctr
       when (hit) {
-        io.resp.takens(w) := Mux(ctr === 3.U || ctr === 4.U, altPred, ctr(2)) // Use altpred on weak taken
-        tageTaken := Mux(ctr === 3.U || ctr === 4.U, altPred, ctr(2))
-        finalAltPred := altPred
+        io.resp.takens(w) := Mux(ctr === 3.U || ctr === 4.U, if4_altPred, ctr(2)) // Use altpred on weak taken
+        if4_tageTaken := Mux(ctr === 3.U || ctr === 4.U, if4_altPred, ctr(2))
+        if4_finalAltPred := if4_altPred
       }
-      provided = provided || hit          // Once hit then provide
-      provider = Mux(hit, i.U, provider)  // Use the last hit as provider
-      altPred = Mux(hit, ctr(2), altPred) // Save current pred as potential altpred
+      if4_provided = if4_provided || hit          // Once hit then provide
+      if4_provider = Mux(hit, i.U, if4_provider)  // Use the last hit as provider
+      if4_altPred = Mux(hit, ctr(2), if4_altPred) // Save current pred as potential altpred
     }
-    io.resp.hits(w) := provided
-    io.meta(w).provider.valid := provided
-    io.meta(w).provider.bits := provider
-    io.meta(w).altDiffers := finalAltPred =/= io.resp.takens(w)
-    io.meta(w).providerU := resps(provider)(w).bits.u
-    io.meta(w).providerCtr := resps(provider)(w).bits.ctr
-    io.meta(w).taken := tageTaken
+    io.resp.hits(w) := if4_provided
+    io.meta(w).provider.valid := if4_provided
+    io.meta(w).provider.bits := if4_provider
+    io.meta(w).altDiffers := if4_finalAltPred =/= io.resp.takens(w)
+    io.meta(w).providerU := if4_resps(if4_provider)(w).bits.u
+    io.meta(w).providerCtr := if4_resps(if4_provider)(w).bits.ctr
+    io.meta(w).taken := if4_tageTaken
 
     // Create a mask fo tables which did not hit our query, and also contain useless entries
     // and also uses a longer history than the provider
-    val allocatableSlots = (VecInit(resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
-      ~(LowerMask(UIntToOH(provider), TageNTables) & Fill(TageNTables, provided.asUInt))
+    val allocatableSlots = (VecInit(if4_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
+      ~(LowerMask(UIntToOH(if4_provider), TageNTables) & Fill(TageNTables, if4_provided.asUInt))
     )
     val allocLFSR = LFSR64()(TageNTables - 1, 0)
     val firstEntry = PriorityEncoder(allocatableSlots)
@@ -525,12 +525,12 @@ class Tage extends BaseTage {
     scMeta := DontCare
     val scTableSums = VecInit(
       (0 to 1) map { i => {
-          // val providerCtr = resps(provider)(w).bits.ctr.zext()
+          // val providerCtr = if4_resps(if4_provider)(w).bits.ctr.zext()
           // val pvdrCtrCentered = (((providerCtr - 4.S) << 1) + 1.S) << 3
           // sum += pvdrCtrCentered
           if (EnableSC) {
             (0 until SCNTables) map { j => 
-              scTables(j).getCenteredValue(scResps(j)(w).ctr(i))
+              scTables(j).getCenteredValue(if4_scResps(j)(w).ctr(i))
             } reduce (_+_) // TODO: rewrite with adder tree
           }
           else 0.S
@@ -539,21 +539,21 @@ class Tage extends BaseTage {
     )
 
     if (EnableSC) {
-      scMeta.tageTaken := tageTaken
-      scMeta.scUsed := provided
-      scMeta.scPred := tageTaken
+      scMeta.tageTaken := if4_tageTaken
+      scMeta.scUsed := if4_provided
+      scMeta.scPred := if4_tageTaken
       scMeta.sumAbs := 0.U
-      when (provided) {
-        val providerCtr = resps(provider)(w).bits.ctr.zext()
+      when (if4_provided) {
+        val providerCtr = if4_resps(if4_provider)(w).bits.ctr.zext()
         val pvdrCtrCentered = ((((providerCtr - 4.S) << 1).asSInt + 1.S) << 3).asSInt
-        val totalSum = scTableSums(tageTaken.asUInt) + pvdrCtrCentered
+        val totalSum = scTableSums(if4_tageTaken.asUInt) + pvdrCtrCentered
         val sumAbs = totalSum.abs().asUInt
         val sumBelowThreshold = totalSum.abs.asUInt < useThreshold
         val scPred = totalSum >= 0.S
         scMeta.sumAbs := sumAbs
-        scMeta.ctrs   := VecInit(scResps.map(r => r(w).ctr(tageTaken.asUInt)))
+        scMeta.ctrs   := VecInit(if4_scResps.map(r => r(w).ctr(if4_tageTaken.asUInt)))
         for (i <- 0 until SCNTables) {
-          XSDebug(RegNext(io.s3Fire), p"SCTable(${i.U})(${w.U}): ctr:(${scResps(i)(w).ctr(0)},${scResps(i)(w).ctr(1)})\n")
+          XSDebug(RegNext(io.s3Fire), p"SCTable(${i.U})(${w.U}): ctr:(${if4_scResps(i)(w).ctr(0)},${if4_scResps(i)(w).ctr(1)})\n")
         }
         XSDebug(RegNext(io.s3Fire), p"SC(${w.U}): pvdCtr(${providerCtr}), pvdCentred(${pvdrCtrCentered}), totalSum(${totalSum}), abs(${sumAbs}) useThres(${useThreshold}), scPred(${scPred})\n")
         // Use prediction from Statistical Corrector
@@ -664,7 +664,7 @@ class Tage extends BaseTage {
     XSDebug(RegNext(io.s3Fire), "s3FireOnLastCycle: resp: pc=%x, hist=%x, hits=%b, takens=%b\n",
       debug_pc_s3, debug_hist_s3, io.resp.hits.asUInt, io.resp.takens.asUInt)
     for (i <- 0 until TageNTables) {
-      XSDebug(RegNext(io.s3Fire), "TageTable(%d): valids:%b, resp_ctrs:%b, resp_us:%b\n", i.U, VecInit(resps(i).map(_.valid)).asUInt, Cat(resps(i).map(_.bits.ctr)), Cat(resps(i).map(_.bits.u)))
+      XSDebug(RegNext(io.s3Fire), "TageTable(%d): valids:%b, resp_ctrs:%b, resp_us:%b\n", i.U, VecInit(if4_resps(i).map(_.valid)).asUInt, Cat(if4_resps(i).map(_.bits.ctr)), Cat(if4_resps(i).map(_.bits.u)))
     }
     XSDebug(io.update.valid, "update: pc=%x, fetchpc=%x, cycle=%d, hist=%x, taken:%d, misPred:%d, bimctr:%d, pvdr(%d):%d, altDiff:%d, pvdrU:%d, pvdrCtr:%d, alloc(%d):%d\n",
       u.pc, u.pc - (bri.fetchIdx << 1.U), bri.debug_tage_cycle,  updateHist, u.taken, u.isMisPred, bri.bimCtr, m.provider.valid, m.provider.bits, m.altDiffers, m.providerU, m.providerCtr, m.allocate.valid, m.allocate.bits)