This commit moves load/store reservation stations into the first
ExuBlock (or calling it IntegerBlock). The unnecessary dispatch module
is also removed from CtrlBlock.

Now the module organization becomes:
* ExuBlock: Int RS, Load/Store RS, Int RF, Int FUs
* ExuBlock_1: Fp RS, Fp RF, Fp FUs
* MemBlock: Load/Store FUs

Besides, load queue has 80 entries and store queue has 64 entries now.

* Refactor cache params

* L2: support multi-bank

* fix l2 size

* remove 'IgnoreNode'

* bump difftest and huancun

This commit fixes a bug that causes pc to be wrong values when a jump is
blocked for issue and a new jump instruction enters reservation station.
When the jump for issue is blocked, we should latch its pc value because
the entry has been deallocated from rs (and pc no longer exists in the
pc mem).

* change ROB to 256 entries
* change physical register file to 192 entries
* re-organize reservation stations, function units and regfile

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

* scripts,ci: fix broken multi-core build

* Fix debugIntNode on multi core

This commit adds storage for PC in JUMP reservation station. Jalr needs
four operands now, including rs1, pc, jalr_target and imm. Since Jump
currently stores two operands and imm, we have to allocate extra space
to store the one more extra operand for jalr.

It should be optimized later (possibly by reading jalr_target when
issuing the instruction).

This commit also adds regression check for PC usages. PC should not
enter decode stage.

* L1D: provide independent meta array for load pipe

* misc: reorg files in cache dir

* chore: reorg l1d related files

* bump difftest: use clang to compile verialted files

* dcache: add BankedDataArray

* dcache: fix data read way_en

* dcache: fix banked data wmask

* dcache: replay conflict correctly

 When conflict is detected:
* Report replay
* Disable fast wakeup

* dcache: fix bank addr match logic

* dcache: add bank conflict perf counter

* dcache: fix miss perf counters

* chore: make lsq data print perttier

* dcache: enable banked ecc array

* dcache: set dcache size to 128KB

* dcache: read mainpipe data from banked data array

* dcache: add independent mainpipe data read port

* dcache: revert size change

* Size will be changed after main pipe refactor

* Merge remote-tracking branch 'origin/master' into l1-size

* dcache: reduce banked data load conflict

* MainPipe: ReleaseData for all replacement even if it's clean

* dcache: set dcache size to 128KB

BREAKING CHANGE: l2 needed to provide right vaddr index to probe l1,
and it has to help l1 to avoid addr alias problem

* chore: fix merge conflict

* Change L2 to non-inclusive / Add alias bits in L1D

* debug: hard coded dup data array for debuging

* dcache: fix ptag width

* dcache: fix amo main pipe req

* dcache: when probe, use vaddr for main pipe req

* dcache: include vaddr in atomic unit req

* dcache: fix get_tag() function

* dcache: fix writeback paddr

* huancun: bump version

* dcache: erase block offset bits in release addr

* dcache: do not require probe vaddr != 0

* dcache: opt banked data read timing

* bump huancun

* dcache: fix atom unit pipe req vaddr

* dcache: simplify main pipe writeback_vaddr

* bump huancun

* dcache: remove debug data array

* Turn on all usr bits in L1

* Bump huancun

* Bump huancun

* enable L2 prefetcher

* bump huancun

* set non-inclusive L2/L3 + 128KB L1 as default config

* Use data in TLBundleB to hint ProbeAck beeds data

* mmu.l2tlb: mem_resp now fills multi mq pte buffer

mq entries can just deq without accessing l2tlb cache

* dcache: handle dirty userbit

* bump huancun

* chore: l1 cache code clean up

* Remove l1plus cache
* Remove HasBankedDataArrayParameters

* Add bus pmu between L3 and Mem

* bump huncun

* dcache: fix l1 probe index generate logic

* Now right probe index will be used according to the len of alias bits

* dcache: clean up amo pipeline

* DCacheParameter rowBits will be removed in the future, now we set it to 128
to make dcache work

* dcache: fix amo word index

* bump huancun
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>
Co-authored-by: NTangDan <tangdan@ict.ac.cn>
Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>

This commit applys Definition and Instance for some modules. Refer to
https://github.com/chipsalliance/chisel3/pull/2045.

BPU: Modify ubtb to direct mapped from fully associative

IFU: add more performance counters and raise access fault for mmio req temporarily

* icache replacement policy moniter

* ifu miss situation moniter

* icache miss rate

This commit optimizes ALUOpType to 7 bits. Alu timing will be checked
later.

We also apply some misc changes including:

* Move REVB, PACK, PACKH, PACKW to ALU

* Add fused logicZexth, addwZext, addwSexth

* Add instruction fusion test cases to CI

* Bmu: support zbk* instructions

* ci: add zbk* instruction test

This commit explitly imports freechips..rocketchip.util.property.cover
for compatibility reasons, since chisel3 now has a cover statement.

This commit changes how compressed move instructions are decoded.
From RISC-V spec, mv pesudoinstruction should be addi. However,
previously RVC decoder changes compressed mv to add.

Move elimination finds move instructions by addi opcode. Compressed
move instructions can now be eliminated.

* New SRT4 divider that may improve timing

See "Digital reurrence dividers with reduced logical depth"

* SRT16 Int Divider that is working properly

* Fix bug related to div 1

* Timing improved version of SRT16 int divider

* Add copyright and made some minor changes

* Fix bugs related to div 0

* Fix another div 0 bug

* Fix another special case bug

backend, freelist: optimize critical path & verilog code size in MEFreeList

- optimize free/allocate/walk/flush logic in MEFreeList
- remove useless assertions
- decrease length of generated verilog file

instead of chisel var in MEFreeList.scala

This commit adds performance counters for function units that have
feedback to reservation stations, including FMA, Load and Store.
We add performance counters to show how many instructions are issued for
multiple times.

FTQ: Fix the false hit bug when run mcf

This commit splits FMA instructions into FMUL and FADD for execution.

When the first two operands are ready, an FMA instruction can be issued
and the intermediate result will be written back to RS after two cycles.
Since RS currently has DataArray to store the operands, we reuse it to
store the intermediate FMUL result.

When an FMA enters deq stage and leaves RS with only two operands, we
mark it as midState ready at this clock cycle T0.

If the instruction's third operand becomes ready at T0, it can be
selected at T1 and issued at T2, when FMUL is also finished. The
intermediate result will be sent to FADD instead of writing back to RS.
If the instruction's third operand becomes ready later, we have the data
in DataArray or at DataArray's write port. Thus, it's ok to set midState
ready at clock cycle T0.

The separation of FMA instructions will increase issue pressure since RS
needs to issue more times. However, it larges reduce FMA latency if many
FMA instructions are waiting for the third operand.

This commit adds load balance strategy in issue selection logic for
reservation stations.

Previously we have a load balance option in ExuBlock, but it cannot work
if the function units have feedbacks to RS. In this commit it is
removed.

This commit adds a victim index option for oldestFirst. For LOAD, the
first issue port has better performance and thus we set the victim index
to 0. For other function units, we use the last issue port.

1) generate ptr and preg in a vec first
2) use renameEnable to replace common parts in allocating logic

This commit adds timer counters for some important pipeline stages,
including rename, dispatch, dispatch2, select, issue, execute, commit.
We add performance counters for different types of instructions to see
the latency in different pipeline stages.

This PR replaces coremark, microbench, and all perfromence test workloads by corresponding RV64GCB workloads.

1) bug fix: updateArchRefCounter should be related with pdest, not
old_pdest
2) remove complicated logic of headPtr recovery when flushing

Fix fencei and physical tag bugs in ICache