* AXIFlash: use blackbox to rebuild flash

* device.cpp: add init_flash

* Add flash.cpp for DPI-C funtion

* Flash: use USE_BIN to enable FI from flash

* AXIFlash: delete original flash

* L2/L3: set replacement policy to plru

* Bump l2

Previously in commit 298aa395,
we incorrectly set simulation freq to 1,000,000.

L2 and L3 Only enablePerf when XSCore enables perf.

* l2,timing: bump l2/l3 cache

This will necessarily add several cycles to L2/L3 cache responsing time.

* l2,l3: bump timing tweaks

Resolved timeout in debian boot.
Remove repeat feature to avoid directory disturbing
(repeat allows to use previous tag and victim info which is dangerous).

TODO:
- [ ] Another directory atomicity weakness that heavy l1 release can
      overwrite l3tol2 probe directory update, for example:
      l1.rel.TtoB write dirty -> l1.rel.BtoN readout dirty then writeback
               l2.probeAck.BtoB write non-dirty (not saved)
      l3 think l2 is branch, but l2 is still trunk.
      But forbid nestB and nestC can cause deadlock...
- [ ] Delay bankedStore one more cycle for L3 large sram timing.

* l2,l3: change mshr amount to 15

* RS: fix bug that fp src's flushed enqueue conflicts with next enqueue

* RS: fix bug that ctrl's flushed enqueue conflicts with next enqueue

XSPerfAccumulate: sum up performance values.
XSPerfHistogram: count the occurrence of performance values, split them
into bins, so that we can estimate their distribution.
XSPerfMax: get max of performance values.

Not tested yet.

Added:
* L1 MSHR occupation
* L1 MSHR latency
* L1 Load Miss latency
* L1 Store latency
* L1 Store occupation
* L1 Load req count

Now we can put a performance value into several bins and count them.
In this way, we can get a distribution of this performance value.

* perf: set acc arg of XSPerf as false by default

* perf: add write-port competition counter for intBlock & floatBlock

* perf: remove prefix of perf signal

* perf: add perf-cnt for interface between frontend & backend

* perf: modify perf-cnt for prefetchers

* Ftq: bypass 'commit state' to fix dequeue bug

* perf: uptimize perf-cnt in ctrlblock & ftq

* perf: fix compilation problem in ftq

* perf: remove duplicate perf-cnt

* perf: calcu extra walk cycle exceeding frontend flush bubble

* Revert "perf: calcu extra walk cycle exceeding frontend flush bubble"

This reverts commit 2c30e9896b6af93a34e2d8d78055d810ebd0ac70.

* perf: add perf-cnt for ifu

* perf: add perf-cnt for rs

* RS: optimize numExist signal

* RS: fix some typo

* perf: add QueuePerf util to monitor usage info of queues

* perf: remove some duprecate perfcnt

* MissQueue: add perf cnt for inflight entries in maximum

* MissQueue: max_inflight ignores cycles when missQueue is empty

This allows the software to determine whether an address
can be read or written.

* add perf counters for btb and ubtb
* update btb only on not hit or jalr mispredicts to reduce write stalls

just record the tlb result(access and miss) of first issue by add
signal isFirstIssue (isFirstIssue = cntCountQueue(i) === 0.U)

* DCacheWrapper: MainPipe use read port 1 to ease congestion

* MainPipe: do not consider congestion with ldu0 read when disabling fast wakeup