l2,timing: bump l2/l3 cache (#652)

* l2,timing: bump l2/l3 cache

This will necessarily add several cycles to L2/L3 cache responsing time.

* l2,l3: bump timing tweaks

Resolved timeout in debian boot.
Remove repeat feature to avoid directory disturbing
(repeat allows to use previous tag and victim info which is dangerous).

TODO:
- [ ] Another directory atomicity weakness that heavy l1 release can
      overwrite l3tol2 probe directory update, for example:
      l1.rel.TtoB write dirty -> l1.rel.BtoN readout dirty then writeback
               l2.probeAck.BtoB write non-dirty (not saved)
      l3 think l2 is branch, but l2 is still trunk.
      But forbid nestB and nestC can cause deadlock...
- [ ] Delay bankedStore one more cycle for L3 large sram timing.

* l2,l3: change mshr amount to 15

block-inclusivecache-sifive @ df9d8583

-Subproject commit 54a97b8b9325921ea7cdaa45db7519d9a3666da5
+Subproject commit df9d8583fe131241b1b3dbc787e46ca95d9b3afc

src/main/scala/top/Top.scala

@@ -33,6 +33,7 @@ class XSCoreWithL2()(implicit p: config.Parameters) extends LazyModule
       cacheName = s"L2"
     ),
     InclusiveCacheMicroParameters(
+      memCycles = 25,
       writeBytes = 32
     )
   ))
@@ -225,6 +226,7 @@ class XSTop()(implicit p: config.Parameters) extends BaseXSSoc()
       cacheName = "L3"
     ),
     InclusiveCacheMicroParameters(
+      memCycles = 25,
       writeBytes = 32
     )
   )).node