- 12 5月, 2021 2 次提交
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由 Jiawei Lin 提交于
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由 William Wang 提交于
* Configs: add MinimalFPGAConfig * TODO: change cache parameters * Chore: add parameter print * README: add simulation usage Currently, XiangShan does not support NOOP FPGA. FPGA related instructions are removed * Configs: limit frontend width in MinimalConfig * MinimalConfig: limit L1/L2 cache size * MinimalConfig: limit ptw size, disable L2 * MinimalConfig: limit L3 size * Sbuffer: force trigger write if sbuffer fulls
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- 11 5月, 2021 2 次提交
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由 Yinan Xu 提交于
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由 William Wang 提交于
* LoadQueue: send stFtqIdx via rollback request * It will make it possible for setore set to update its SSIT * StoreSet: setup store set update req * StoreSet: add store set identifier table (SSIT) * StoreSet: add last fetched store table (LFST) * StoreSet: put SSIT into decode stage * StoreSet: put LFST into dispatch1 * Future work: optimize timing * RS: store rs now supports delayed issue * StoreSet: add perf counter * StoreSet: fix SSIT update logic * StoreSet: delay LFST update input for 1 cycle * StoreSet: fix LFST update logic * StoreSet: fix LFST raddr width * StoreSet: do not force store in ss issue in order Classic store set requires store in the same store set issue in seq. However, in current micro-architecture, such restrict will lead to severe perf lost. We choose to disable it until we find another way to fix it. * StoreSet: support ooo store in the same store set * StoreSet: fix store set merge logic * StoreSet: check earlier store when read LFST * If store-load pair is in the same dispatch bundle, loadWaitBit should also be set for load * StoreSet: increase default SSIT flush period * StoreSet: fix LFST read logic * Fix commit c0e541d1 * StoreSet: add StoreSetEnable parameter * RSFeedback: add source type * StoreQueue: split store addr and store data * StoreQueue: update ls forward logic * Now it supports splited addr and data * Chore: force assign name for load/store unit * RS: add rs'support for store a-d split * StoreQueue: fix stlf logic * StoreQueue: fix addr wb sq update logic * AtomicsUnit: support splited a/d * Parameters: disable store set by default * WaitTable: wait table will not cause store delay * WaitTable: recover default reset period to 2^17 * Fix dev-stad merge conflict * StoreSet: enable storeset * RS: disable store rs delay logic CI perf shows that current delay logic will cause perf loss. Disable unnecessary delay logic will help. To be more specific, `io.readyVec` caused the problem. It will be updated in future commits. * RS: opt select logic with load delay (ldWait) * StoreSet: disable 2-bit lwt Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
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- 09 5月, 2021 2 次提交
- 07 5月, 2021 5 次提交
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由 William Wang 提交于
Config: add MinimalConfig
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由 LinJiawei 提交于
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由 LinJiawei 提交于
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由 Yinan Xu 提交于
* CI: put perf result in xs-perf/cmtsha-time * CI: make result dir before start perfing * Update emu.yml * ci: add bash scripts * scripts: add xiangshan wrapper Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
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由 Yinan Xu 提交于
This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
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- 06 5月, 2021 2 次提交
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由 William Wang 提交于
MinimalConfig limited queues' size, disabled TAGE to limit generated verilog size Usage: change `config = DefaultConfig` to `config = MinimalConfig` in Top.scala / SimTop.scala
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由 Lemover 提交于
* [WIP] Backend: add mul to fast wake-up * Backend: handle mul wb priority and fix wrong delay * RS: devide fastwakeup and nonBlocked(they were binded)
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- 05 5月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 04 5月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit fixes the bug when redirect.valid and the last valid instruction is in the last slot. Previously the tailPtr becomes size.U when there're no instructions before headPtr. It works fine when DispatchQueueSize is power2.
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- 01 5月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit uses Vec for lsrc, psrc, srcState and srcType in MicroOp bundle. This makes uop easier to access.
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- 30 4月, 2021 3 次提交
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由 William Wang 提交于
* emu: add --no-perf-counter option Now perf counter result print will no longer be controlled by --log-begin / --log-end * emu: add --force-dump-result option This option will override log_end to -1 when simulation finishs. --no-perf-counter option is removed.
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由 Yinan Xu 提交于
In this commit, we add support for using DPI-C calls to replace DCache, PTW and L1plusCache. L2Cache and L3 Cache are also allowed to be ignored or bypassed. Configurations are controlled by useFakeDCache, useFakePTW, useFakeL1plusCache, useFakeL2Cache and useFakeL3Cache. However, some configurations may not work correctly.
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由 William Wang 提交于
* RSFeedback: add source type * StoreQueue: split store addr and store data * StoreQueue: update ls forward logic * Now it supports splited addr and data * Chore: force assign name for load/store unit * RS: add rs'support for store a-d split * StoreQueue: fix stlf logic * StoreQueue: fix addr wb sq update logic * AtomicsUnit: support splited a/d * StoreQueue: add sbuffer enq condition assertion Store data op (std) may still be invalid after store addr op's (sta) commitment, so datavalid needs to be checked before commiting store data to sbuffer Note that at current commit a non-completed std op for a commited store may exist. We should make sure that uop will not be cancelled by a latter branch mispredict. More work to be done! * Roq: add std/sta split writeback logic Now store will commit only if both sta & std have been writebacked Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
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- 29 4月, 2021 2 次提交
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由 wakafa 提交于
* difftest: revise coreid assignment * nemuproxy: compatible for smp difftest * difftest: fix goldenMem initialization problem * difftest: goldenMem update works * difftest: api compatible for modified nemu * difftest: support load check for smp difftest * verification is required later * misc: remove unused xstrap wiring * Remove unused code * difftest: add latch for difftest-loadevent * misc: update inclusivecache * difftest: reset resp for sbuffer & atomic-unit to avoid duplicate update of goldenMem * difftest: dump coreid when difftest failed * difftest: dump corresponding memory of another core when smp difftest failed * Only works for dual-core * difftest: fix interrupt handler * difftest: cleanup code * roq: remove legacy signal for difftest
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由 Lemover 提交于
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- 28 4月, 2021 1 次提交
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由 Lemover 提交于
* Perf: add perf counter for addr gen, across page or not * Perf: add perf counter for addr gen, just record first issue
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- 26 4月, 2021 3 次提交
- 25 4月, 2021 3 次提交
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由 wakafa 提交于
No functional affect is introduced.
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由 wakafa 提交于
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由 Jiawei Lin 提交于
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- 24 4月, 2021 9 次提交
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由 William Wang 提交于
* Emu: stop sim if assertion is triggered * Difftest: fix record_inst wdata width * Difftest: fix xs_assert * fix assert bug in L3 Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>
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由 Yinan Xu 提交于
Refine makefile
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由 Zihao Yu 提交于
* For verilator installed by package manager, it may not be configured with ccache. So we check it at runtime.
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
* this can switch to different reference design without re-compile emu
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
* --threads 1 will create a multi-threaded model but with only one thread, which is unnecessary and will reduce performance
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由 Zihao Yu 提交于
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由 Yinan Xu 提交于
MMIO should never hit in DCache. However, DCache does not guarantee the miss is strictly according to the vaddr, paddr provided by the pipeline, when the load is killed. That is, DCache may response valid = false and miss = false when the MMIO instruction is accessed and then killed. For instructions with exceptions, it will cause flush when it retires and not cause errors.
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- 23 4月, 2021 2 次提交
- 22 4月, 2021 1 次提交
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由 Yinan Xu 提交于
In this commit, we add performance counters for dispatch and issue stages to track the number of instructions dispatched and issued. Active regfile read ports are counted as ready instruction source registers.
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