1. 12 5月, 2021 2 次提交
    • J
      Update mill and rocket-chip (#810) · 16cf0dd4
      Jiawei Lin 提交于
      16cf0dd4
    • W
      Configs: update MinimalConfig for FPGA (#809) · 05f23f57
      William Wang 提交于
      * Configs: add MinimalFPGAConfig
      
      * TODO: change cache parameters
      
      * Chore: add parameter print
      
      * README: add simulation usage
      
      Currently, XiangShan does not support NOOP FPGA. FPGA related
      instructions are removed
      
      * Configs: limit frontend width in MinimalConfig
      
      * MinimalConfig: limit L1/L2 cache size
      
      * MinimalConfig: limit ptw size, disable L2
      
      * MinimalConfig: limit L3 size
      
      * Sbuffer: force trigger write if sbuffer fulls
      05f23f57
  2. 11 5月, 2021 2 次提交
    • Y
      test,vcs: call $finish when difftest fails (#808) · 632fc81b
      Yinan Xu 提交于
      632fc81b
    • W
      backend,mem: add Store Sets memory dependence predictor (#796) · de169c67
      William Wang 提交于
      * LoadQueue: send stFtqIdx via rollback request
      
      * It will make it possible for setore set to update its SSIT
      
      * StoreSet: setup store set update req
      
      * StoreSet: add store set identifier table (SSIT)
      
      * StoreSet: add last fetched store table (LFST)
      
      * StoreSet: put SSIT into decode stage
      
      * StoreSet: put LFST into dispatch1
      
      * Future work: optimize timing
      
      * RS: store rs now supports delayed issue
      
      * StoreSet: add perf counter
      
      * StoreSet: fix SSIT update logic
      
      * StoreSet: delay LFST update input for 1 cycle
      
      * StoreSet: fix LFST update logic
      
      * StoreSet: fix LFST raddr width
      
      * StoreSet: do not force store in ss issue in order
      
      Classic store set requires store in the same store set issue in seq.
      However, in current micro-architecture, such restrict will lead to
      severe perf lost. We choose to disable it until we find another way
      to fix it.
      
      * StoreSet: support ooo store in the same store set
      
      * StoreSet: fix store set merge logic
      
      * StoreSet: check earlier store when read LFST
      
      * If store-load pair is in the same dispatch bundle, loadWaitBit should
      also be set for load
      
      * StoreSet: increase default SSIT flush period
      
      * StoreSet: fix LFST read logic
      
      * Fix commit c0e541d1
      
      * StoreSet: add StoreSetEnable parameter
      
      * RSFeedback: add source type
      
      * StoreQueue: split store addr and store data
      
      * StoreQueue: update ls forward logic
      
      * Now it supports splited addr and data
      
      * Chore: force assign name for load/store unit
      
      * RS: add rs'support for store a-d split
      
      * StoreQueue: fix stlf logic
      
      * StoreQueue: fix addr wb sq update logic
      
      * AtomicsUnit: support splited a/d
      
      * Parameters: disable store set by default
      
      * WaitTable: wait table will not cause store delay
      
      * WaitTable: recover default reset period to 2^17
      
      * Fix dev-stad merge conflict
      
      * StoreSet: enable storeset
      
      * RS: disable store rs delay logic
      
      CI perf shows that current delay logic will cause perf loss. Disable
      unnecessary delay logic will help.
      
      To be more specific, `io.readyVec` caused the problem. It will be
      updated in future commits.
      
      * RS: opt select logic with load delay (ldWait)
      
      * StoreSet: disable 2-bit lwt
      Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
      de169c67
  3. 09 5月, 2021 2 次提交
  4. 07 5月, 2021 5 次提交
  5. 06 5月, 2021 2 次提交
    • W
      Config: add MinimalConfig · ec5c8ac7
      William Wang 提交于
      MinimalConfig limited queues' size, disabled TAGE to limit generated
      verilog size
      
      Usage: change `config = DefaultConfig` to `config = MinimalConfig`
      in Top.scala / SimTop.scala
      ec5c8ac7
    • L
      Backend: add mul to fast wakeup (#769) · 22deac3a
      Lemover 提交于
      * [WIP] Backend: add mul to fast wake-up
      
      * Backend: handle mul wb priority and fix wrong delay
      
      * RS: devide fastwakeup and nonBlocked(they were binded)
      22deac3a
  6. 05 5月, 2021 1 次提交
  7. 04 5月, 2021 1 次提交
    • Y
      DispatchQueue: wrap around tailPtr index when redirect (#800) · 695364a3
      Yinan Xu 提交于
      This commit fixes the bug when redirect.valid and the last valid instruction is in the last slot.
      Previously the tailPtr becomes size.U when there're no instructions before headPtr. It works fine
      when DispatchQueueSize is power2.
      695364a3
  8. 01 5月, 2021 1 次提交
  9. 30 4月, 2021 3 次提交
    • W
      emu: add --force-dump-result option (#791) · a9749791
      William Wang 提交于
      * emu: add --no-perf-counter option
      
      Now perf counter result print will no longer be controlled by
      --log-begin / --log-end
      
      * emu: add --force-dump-result option
      
      This option will override log_end to -1 when simulation finishs.
      --no-perf-counter option is removed.
      a9749791
    • Y
      cache: support fake dcache, ptw, l1pluscache, l2cache and l3cache (#795) · 9d5a2027
      Yinan Xu 提交于
      In this commit, we add support for using DPI-C calls to replace
      DCache, PTW and L1plusCache. L2Cache and L3 Cache are also allowed to
      be ignored or bypassed. Configurations are controlled by useFakeDCache,
      useFakePTW, useFakeL1plusCache, useFakeL2Cache and useFakeL3Cache.
      However, some configurations may not work correctly.
      9d5a2027
    • W
      MemBlock: split store addr and store data (#781) · 1b7adedc
      William Wang 提交于
      * RSFeedback: add source type
      
      * StoreQueue: split store addr and store data
      
      * StoreQueue: update ls forward logic
      
      * Now it supports splited addr and data
      
      * Chore: force assign name for load/store unit
      
      * RS: add rs'support for store a-d split
      
      * StoreQueue: fix stlf logic
      
      * StoreQueue: fix addr wb sq update logic
      
      * AtomicsUnit: support splited a/d
      
      * StoreQueue: add sbuffer enq condition assertion
      
      Store data op (std) may still be invalid after store addr op's (sta)
      commitment, so datavalid needs to be checked before commiting
      store data to sbuffer
      
      Note that at current commit a non-completed std op for a
      commited store may exist. We should make sure that uop
      will not be cancelled by a latter branch mispredict. More work
      to be done!
      
      * Roq: add std/sta split writeback logic
      
      Now store will commit only if both sta & std have been writebacked
      Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
      1b7adedc
  10. 29 4月, 2021 2 次提交
    • W
      difftest: support SMP difftest (#786) · 68f25d38
      wakafa 提交于
      * difftest: revise coreid assignment
      
      * nemuproxy: compatible for smp difftest
      
      * difftest: fix goldenMem initialization problem
      
      * difftest: goldenMem update works
      
      * difftest: api compatible for modified nemu
      
      * difftest: support load check for smp difftest
      * verification is required later
      
      * misc: remove unused xstrap wiring
      
      * Remove unused code
      
      * difftest: add latch for difftest-loadevent
      
      * misc: update inclusivecache
      
      * difftest: reset resp for sbuffer & atomic-unit to avoid duplicate update
      of goldenMem
      
      * difftest: dump coreid when difftest failed
      
      * difftest: dump corresponding memory of another core when smp difftest failed
      * Only works for dual-core
      
      * difftest: fix interrupt handler
      
      * difftest: cleanup code
      
      * roq: remove legacy signal for difftest
      68f25d38
    • L
      Perf: add perf counter to record rs wake up source (#792) · b6220f0d
      Lemover 提交于
      b6220f0d
  11. 28 4月, 2021 1 次提交
  12. 26 4月, 2021 3 次提交
  13. 25 4月, 2021 3 次提交
  14. 24 4月, 2021 9 次提交
  15. 23 4月, 2021 2 次提交
  16. 22 4月, 2021 1 次提交
    • Y
      Add dispatch and issue performance counters (#770) · a338f247
      Yinan Xu 提交于
      In this commit, we add performance counters for dispatch and issue stages
      to track the number of instructions dispatched and issued. Active regfile
      read ports are counted as ready instruction source registers.
      a338f247