Rewrite arg parser

src/main/scala/top/ArgParser.scala

+package top
+
+import chipsalliance.rocketchip.config.{Config, Parameters}
+import system.SoCParamsKey
+import xiangshan.DebugOptionsKey
+
+import scala.annotation.tailrec
+import scala.sys.exit
+
+object ArgParser {
+  // TODO: add more explainations
+  val usage =
+    """
+      |XiangShan Options
+      |--xs-help                  print this help message
+      |--config <ConfigClassName>
+      |--num-cores <Int>
+      |--dual-core                same as '--num-cores 2'
+      |--with-dramsim3
+      |--disable-log
+      |--disable-perf
+      |""".stripMargin
+
+  def getConfigByName(confString: String): Parameters = {
+    var prefix = "top." // default package is 'top'
+    if(confString.contains('.')){ // already a full name
+      prefix = ""
+    }
+    val c = Class.forName(prefix + confString).getConstructor(Integer.TYPE)
+    c.newInstance(1.asInstanceOf[Object]).asInstanceOf[Parameters]
+  }
+  def parse(args: Array[String]): (Parameters, Array[String]) = {
+    val default = new DefaultConfig(1)
+    var firrtlOpts = Array[String]()
+    @tailrec
+    def nextOption(config: Parameters, list: List[String]): Parameters = {
+      list match {
+        case Nil => config
+        case "--xs-help" :: tail =>
+          println(usage)
+          if(tail == Nil) exit(0)
+          nextOption(config, tail)
+        case "--config" :: confString :: tail =>
+          nextOption(getConfigByName(confString), tail)
+        case "--num-cores" :: value :: tail =>
+          nextOption(config.alter((site, here, up) => {
+            case SoCParamsKey => up(SoCParamsKey).copy(
+              cores = List.tabulate(value.toInt){ i => up(SoCParamsKey).cores.head.copy(HartId = i) }
+            )
+          }), tail)
+        case "--dual-core" :: tail =>
+          nextOption(config, "--num-cores" :: "2" :: tail)
+        case "--with-dramsim3" :: tail =>
+          nextOption(config.alter((site, here, up) => {
+            case DebugOptionsKey => up(DebugOptionsKey).copy(UseDRAMSim = true)
+          }), tail)
+        case "--disable-log" :: tail =>
+          nextOption(config.alter((site, here, up) => {
+            case DebugOptionsKey => up(DebugOptionsKey).copy(EnableDebug = false)
+          }), tail)
+        case "--disable-perf" :: tail =>
+          nextOption(config.alter((site, here, up) => {
+            case DebugOptionsKey => up(DebugOptionsKey).copy(EnablePerfDebug = false)
+          }), tail)
+        case option :: tail =>
+          // unknown option, maybe a firrtl option, skip
+          firrtlOpts :+= option
+          nextOption(config, tail)
+      }
+    }
+    (nextOption(default, args.toList), firrtlOpts)
+  }
+}

src/main/scala/top/Config.scala → src/main/scala/top/Configs.scala

@@ -20,29 +20,31 @@ class DefaultConfig(n: Int) extends Config((site, here, up) => {
   )
 })
 
-class MinimalConfig(n: Int) extends Config((site, here, up) => {
-  case XLen => 64
-  case DebugOptionsKey => DebugOptions()
-  case SoCParamsKey => SoCParameters(
-    cores = List.tabulate(n){ i => XSCoreParameters(
-      IssQueSize = 8,
-      NRPhyRegs = 80,
-      LoadQueueSize = 16,
-      StoreQueueSize = 16,
-      RoqSize = 32,
-      BrqSize = 8,
-      FtqSize = 16,
-      IBufSize = 16,
-      dpParams = DispatchParameters(
-        IntDqSize = 8,
-        FpDqSize = 8,
-        LsDqSize = 8,
-        IntDqDeqWidth = 4,
-        FpDqDeqWidth = 4,
-        LsDqDeqWidth = 4
-      ),
-      EnableBPD = false, // disable TAGE
-      EnableLoop = false,
+// TODO: disable L2 and L3
+class MinimalConfig(n: Int = 1) extends Config(
+  new DefaultConfig(n).alter((site, here, up) => {
+    case SoCParamsKey => up(SoCParamsKey).copy(
+      cores = up(SoCParamsKey).cores.map(_.copy(
+        HasL2Cache = false,
+        IssQueSize = 8,
+        NRPhyRegs = 80,
+        LoadQueueSize = 16,
+        StoreQueueSize = 16,
+        RoqSize = 32,
+        BrqSize = 8,
+        FtqSize = 16,
+        IBufSize = 16,
+        dpParams = DispatchParameters(
+          IntDqSize = 8,
+          FpDqSize = 8,
+          LsDqSize = 8,
+          IntDqDeqWidth = 4,
+          FpDqDeqWidth = 4,
+          LsDqDeqWidth = 4
+        ),
+        EnableBPD = false, // disable TAGE
+        EnableLoop = false,
+      ))
     )
   })
-})
+)
\ No newline at end of file

src/main/scala/top/Top.scala

@@ -321,12 +321,10 @@ class XSTopWithoutDMA()(implicit p: Parameters) extends BaseXSSoc()
 
 object TopMain extends App {
   override def main(args: Array[String]): Unit = {
-    val numCores = if(args.contains("--dual-core")) 2 else 1
-    val otherArgs = args.filterNot(_ == "--dual-core")
-    implicit val config = new DefaultConfig(numCores)
-    XiangShanStage.execute(otherArgs, Seq(
+    val (config, firrtlOpts) = ArgParser.parse(args)
+    XiangShanStage.execute(firrtlOpts, Seq(
       ChiselGeneratorAnnotation(() => {
-        val soc = LazyModule(new XSTop())
+        val soc = LazyModule(new XSTop()(config))
         soc.module
       })
     ))

src/test/scala/top/SimTop.scala

@@ -71,31 +71,10 @@ class SimTop(implicit p: Parameters) extends Module {
 object SimTop extends App {
 
   override def main(args: Array[String]): Unit = {
-    val useDRAMSim = args.contains("--with-dramsim3")
-    val numCores = if(args.contains("--dual-core")) 2 else 1
-    val disableLog = args.contains("--disable-log")
-    val disablePerf = args.contains("--disable-perf")
-
-    val firrtlArgs = args.
-      filterNot(_ == "--with-dramsim3").
-      filterNot(_ == "--dual-core").
-      filterNot(_ == "--disable-log").
-      filterNot(_ == "--disable-perf")
-
-    val config = new DefaultConfig(numCores).alter((site, here, up) => {
-      case DebugOptionsKey =>
-        val default = up(DebugOptionsKey)
-        DebugOptions(
-          FPGAPlatform = false,
-          EnableDebug = if(disableLog) false else default.EnableDebug,
-          EnablePerfDebug = if(disablePerf) false else default.EnablePerfDebug,
-          UseDRAMSim = if(useDRAMSim) true else default.UseDRAMSim
-        )
-    })
-
+    val (config, firrtlOpts) = ArgParser.parse(args)
     // generate verilog
     XiangShanStage.execute(
-      firrtlArgs,
+      firrtlOpts,
       Seq(
         ChiselGeneratorAnnotation(() => new SimTop()(config))
       )