Backend: add mul to fast wakeup (#769)

* [WIP] Backend: add mul to fast wake-up

* Backend: handle mul wb priority and fix wrong delay

* RS: devide fastwakeup and nonBlocked(they were binded)

src/main/scala/xiangshan/backend/IntegerBlock.scala

@@ -7,7 +7,7 @@ import utils._
 import xiangshan._
 import xiangshan.backend.exu._
 import xiangshan.backend.issue.ReservationStation
-import xiangshan.backend.fu.{CSRFileIO, FenceToSbuffer}
+import xiangshan.backend.fu.{FenceToSbuffer, CSRFileIO, FunctionUnit}
 import xiangshan.backend.regfile.Regfile
 import difftest._
 
@@ -128,7 +128,9 @@ class IntegerBlock
   val readPortIndex = Seq(1, 2, 3, 0, 1, 2, 3)
   val reservationStations = exeUnits.map(_.config).zipWithIndex.map({ case (cfg, i) =>
     var certainLatency = -1
-    if (cfg.hasCertainLatency) {
+    if (cfg == MulDivExeUnitCfg) {// NOTE: dirty code, add mul to fast wake up, but leave div
+      certainLatency = mulCfg.latency.latencyVal.get
+    } else if (cfg.hasCertainLatency) {
       certainLatency = cfg.latency.latencyVal.get
     }
 

src/main/scala/xiangshan/backend/exu/Exu.scala

@@ -59,8 +59,9 @@ case class ExuConfig
       x
     }
   }
-  val hasCertainLatency = latency.latencyVal.nonEmpty
-  val hasUncertainlatency = latency.latencyVal.isEmpty
+  // NOTE: dirty code for MulDivExeUnit
+  val hasCertainLatency = if (name == "MulDivExeUnit") true else latency.latencyVal.nonEmpty
+  val hasUncertainlatency = if (name == "MulDivExeUnit") true else latency.latencyVal.isEmpty
 
   def canAccept(fuType: UInt): Bool = {
     Cat(fuConfigs.map(_.fuType === fuType)).orR()

src/main/scala/xiangshan/backend/exu/Wb.scala

@@ -56,6 +56,7 @@ class Wb(cfgs: Seq[ExuConfig], numOut: Int, isFp: Boolean)(implicit p: Parameter
   val directConnect = io.in.zip(priorities).filter(x => x._2 == 0).map(_._1)
   val mulReq = io.in.zip(priorities).filter(x => x._2 == 1).map(_._1)
   val otherReq = io.in.zip(priorities).filter(x => x._2 > 1).map(_._1)
+  // NOTE: 0 for direct connect; 1 for shared connect but non-blocked; other for shared and may blocked
 
   val portUsed = directConnect.size + mulReq.size
   require(portUsed <= numOut)

src/main/scala/xiangshan/backend/issue/ReservationStation.scala

@@ -92,11 +92,11 @@ class ReservationStation
   feedback: Boolean,
 )(implicit p: Parameters) extends XSModule {
   val iqIdxWidth = log2Up(iqSize)
-  val nonBlocked = fixedDelay >= 0
+  val nonBlocked = if (exuCfg == MulDivExeUnitCfg) false else fixedDelay >= 0
   val srcNum = if (exuCfg == JumpExeUnitCfg) 2 else max(exuCfg.intSrcCnt, exuCfg.fpSrcCnt)
   val fastPortsCnt = fastPortsCfg.size
   val slowPortsCnt = slowPortsCfg.size
-  require(nonBlocked==fastWakeup)
+  // require(nonBlocked==fastWakeup)
 
   val io = IO(new Bundle {
     val numExist = Output(UInt(iqIdxWidth.W))
@@ -227,11 +227,11 @@ class ReservationStationSelect
   feedback: Boolean,
 )(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper{
   val iqIdxWidth = log2Up(iqSize)
-  val nonBlocked = fixedDelay >= 0
+  val nonBlocked = if (exuCfg == MulDivExeUnitCfg) false else fixedDelay >= 0
   val srcNum = if (exuCfg == JumpExeUnitCfg) 2 else max(exuCfg.intSrcCnt, exuCfg.fpSrcCnt)
   val fastPortsCnt = fastPortsCfg.size
   val slowPortsCnt = slowPortsCfg.size
-  require(nonBlocked==fastWakeup)
+  // require(nonBlocked==fastWakeup)
   val replayDelay = VecInit(Seq(1, 1, 1, 5).map(_.U(5.W)))
 
   val io = IO(new Bundle {
@@ -508,11 +508,11 @@ class ReservationStationCtrl
   feedback: Boolean,
 )(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper {
   val iqIdxWidth = log2Up(iqSize)
-  val nonBlocked = fixedDelay >= 0
+  val nonBlocked = if (exuCfg == MulDivExeUnitCfg) false else fixedDelay >= 0
   val srcNum = if (exuCfg == JumpExeUnitCfg) 2 else max(exuCfg.intSrcCnt, exuCfg.fpSrcCnt)
   val fastPortsCnt = fastPortsCfg.size
   val slowPortsCnt = slowPortsCfg.size
-  require(nonBlocked==fastWakeup)
+  // require(nonBlocked==fastWakeup)
 
   val io = IO(new XSBundle {
 
@@ -654,10 +654,12 @@ class ReservationStationCtrl
     val pdest = UInt(PhyRegIdxWidth.W)
     val rfWen = Bool()
     val fpWen = Bool()
+    val fuType = FuType()
     def apply(uop: MicroOp) = {
       this.pdest := uop.pdest
       this.rfWen := uop.ctrl.rfWen
       this.fpWen := uop.ctrl.fpWen
+      this.fuType := uop.ctrl.fuType
       this
     }
   }
@@ -693,7 +695,7 @@ class ReservationStationCtrl
       io.fastUopOut.bits  := fastSentUop
     } else {
       val bpQueue = Module(new BypassQueue(fixedDelay))
-      bpQueue.io.in.valid := selValid
+      bpQueue.io.in.valid := selValid && (if (exuCfg == MulDivExeUnitCfg) fastAsynUop.fuType === FuType.mul else true.B)
       bpQueue.io.in.bits  := fastSentUop
       bpQueue.io.in.bits.roqIdx := fastRoqIdx
       bpQueue.io.redirect := io.redirect
@@ -844,11 +846,11 @@ class ReservationStationData
   feedback: Boolean,
 )(implicit p: Parameters) extends XSModule {
   val iqIdxWidth = log2Up(iqSize)
-  val nonBlocked = fixedDelay >= 0
+  val nonBlocked = if (exuCfg == MulDivExeUnitCfg) false else fixedDelay >= 0
   val srcNum = if (exuCfg == JumpExeUnitCfg) 2 else max(exuCfg.intSrcCnt, exuCfg.fpSrcCnt)
   val fastPortsCnt = fastPortsCfg.size
   val slowPortsCnt = slowPortsCfg.size
-  require(nonBlocked==fastWakeup)
+  // require(nonBlocked==fastWakeup)
 
   val io = IO(new Bundle {
     val srcRegValue = Vec(srcNum, Input(UInt(srcLen.W)))

src/main/scala/xiangshan/package.scala

@@ -439,7 +439,7 @@ package object xiangshan {
     writeIntRf = true,
     writeFpRf = false,
     hasRedirect = false,
-    CertainLatency(3)
+    CertainLatency(2)
   )
 
   val fmacCfg = FuConfig(