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未验证 提交 acd0ebb7 编写于 作者: Y Yinan Xu 提交者： GitHub
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test: add support for VCS simulation (#803) 

This commit adds support for using Synopsys VCS to simulate SimTop.
Difftest is also supported.

For now, we use src/test/vsrc/vcs/top.v as the top-level module.
In the future, we may support VCS slave mode for better scalability.
上级 22deac3a
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Showing with 145 addition and 658 deletion
.gitignore
浏览文件 @ acd0ebb7
......@@ -351,3 +351,12 @@ stale_outputs_checked
*.snapshot
__pycache__
overnight.sh
# VCS files
simv
simv.daidir
ucli.key
stack.info*
*.vpd
*.bin
Makefile
浏览文件 @ acd0ebb7
......@@ -77,34 +77,10 @@ SIM_CXXFILES = $(shell find $(SIM_CSRC_DIR) -name "*.cpp")
DIFFTEST_CSRC_DIR = $(abspath ./src/test/csrc/difftest)
DIFFTEST_CXXFILES = $(shell find $(DIFFTEST_CSRC_DIR) -name "*.cpp")
SIM_VSRC = $(shell find ./src/test/vsrc -name "*.v" -or -name "*.sv")
SIM_VSRC = $(shell find ./src/test/vsrc/common -name "*.v" -or -name "*.sv")
include Makefile.emu
EMU_VCS := simv
VCS_SRC_FILE = $(TOP_V) \
$(BUILD_DIR)/plusarg_reader.v \
$(BUILD_DIR)/SDHelper.v
VCS_TB_DIR = $(abspath ./src/test/vcs)
VCS_TB_FILE = $(shell find $(VCS_TB_DIR) -name "*.c") \
$(shell find $(VCS_TB_DIR) -name "*.v")
VCS_OPTS := -full64 +v2k -timescale=1ns/10ps \
-LDFLAGS -Wl,--no-as-needed \
-sverilog \
+lint=TFIPC-L \
-debug_all +vcd+vcdpluson \
+define+RANDOMIZE_GARBAGE_ASSIGN \
+define+RANDOMIZE_INVALID_ASSIGN \
+define+RANDOMIZE_REG_INIT \
+define+RANDOMIZE_MEM_INIT \
+define+RANDOMIZE_DELAY=1
$(EMU_VCS): $(VCS_SRC_FILE) $(VCS_TB_FILE)
rm -rf csrc
vcs $(VCS_OPTS) $(VCS_SRC_FILE) $(VCS_TB_FILE)
include verilator.mk
include vcs.mk
ifndef NEMU_HOME
$(error NEMU_HOME is not set)
......@@ -150,7 +126,7 @@ cache:
release-lock:
ssh -tt $(REMOTE) 'rm -f $(LOCK)'
clean:
clean: vcs-clean
rm -rf ./build
init:
......
src/test/csrc/vcs/main.cpp 0 → 100644
浏览文件 @ acd0ebb7
#include <common.h>
#include <locale.h>
#include "difftest.h"
#include "device.h"
#include "goldenmem.h"
#include "ram.h"
static bool has_reset = false;
extern "C" void simv_init() {
printf("simv compiled at %s, %s\n", __DATE__, __TIME__);
setlocale(LC_NUMERIC, "");
init_goldenmem();
difftest_init();
init_device();
assert_init();
init_ram("ram.bin");
}
extern "C" void simv_step() {
if (difftest_step()) {
printf("Difftest error\n");
}
}
src/test/vcs/UARTHelper.v 已删除 100644 → 0
浏览文件 @ 22deac3a
import "DPI-C" function void uart_putchar
(
input byte c
);
module UARTHelper(
input clock,
input reset,
input putchar_valid,
input [7:0] putchar_ch,
input getchar_valid,
output [7:0] getchar_ch
);
always@(posedge clock) begin
if(putchar_valid)
uart_putchar(putchar_ch);
end
assign getchar_ch = 'h0;
endmodule
src/test/vcs/common.c 已删除 100644 → 0
浏览文件 @ 22deac3a
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
void xs_assert(long long line) {
printf("Assertion failed at line %lld.\n", line);
}
src/test/vcs/ram.c 已删除 100644 → 0
浏览文件 @ 22deac3a
#include <sys/mman.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#define EMU_RAM_SIZE (256 * 1024 * 1024UL)
static uint64_t *ram;
static long img_size = 0;
void init_ram() {
const char *img = "./ram.bin";
//assert(img != NULL);
printf("The image is %s\n", img);
// initialize memory using Linux mmap
printf("Using simulated %luMB RAM\n", EMU_RAM_SIZE / (1024 * 1024));
ram = (uint64_t *)mmap(NULL, EMU_RAM_SIZE, PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
if (ram == (uint64_t *)MAP_FAILED) {
printf("Cound not mmap 0x%lx bytes\n", EMU_RAM_SIZE);
//assert(0);
}
FILE *fp = fopen(img, "rb");
if (fp == NULL) {
printf("Can not open '%s'\n", img);
//assert(0);
}
fseek(fp, 0, SEEK_END);
img_size = ftell(fp);
if (img_size > EMU_RAM_SIZE) {
img_size = EMU_RAM_SIZE;
}
fseek(fp, 0, SEEK_SET);
fread(ram, img_size, 1, fp);
fclose(fp);
}
void ram_finish() {
munmap(ram, EMU_RAM_SIZE);
}
uint64_t ram_read_helper(uint8_t en, uint64_t rIdx) {
if (en && rIdx >= EMU_RAM_SIZE / sizeof(uint64_t)) {
rIdx %= EMU_RAM_SIZE / sizeof(uint64_t);
}
uint64_t rdata = (en) ? ram[rIdx] : 0;
return rdata;
}
void ram_write_helper(uint64_t wIdx, uint64_t wdata, uint64_t wmask, uint8_t wen) {
if (wen) {
if (wIdx >= EMU_RAM_SIZE / sizeof(uint64_t)) {
printf("ERROR: ram wIdx = 0x%lx out of bound!\n", wIdx);
return;
//assert(wIdx < EMU_RAM_SIZE / sizeof(uint64_t));
}
ram[wIdx] = (ram[wIdx] & ~wmask) | (wdata & wmask);
}
}
src/test/vcs/ram.v 已删除 100644 → 0
浏览文件 @ 22deac3a
import "DPI-C" function void ram_write_helper
(
input longint wIdx,
input longint wdata,
input longint wmask,
input bit wen
);
import "DPI-C" function longint ram_read_helper
(
input bit en,
input longint rIdx
);
import "DPI-C" function void init_ram
(
);
module RAMHelper(
input clk,
input en,
input [63:0] rIdx,
output [63:0] rdata,
input [63:0] wIdx,
input [63:0] wdata,
input [63:0] wmask,
input wen
);
initial begin
init_ram();
end
assign rdata = ram_read_helper(en, rIdx);
always @(posedge clk) begin
ram_write_helper(wIdx, wdata, wmask, wen && en);
end
endmodule
src/test/vcs/sdcard.c 已删除 100644 → 0
浏览文件 @ 22deac3a
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
FILE *fp = NULL;
void sd_setaddr(uint32_t addr) {
fseek(fp, addr, SEEK_SET);
//printf("set addr to 0x%08x\n", addr);
//assert(0);
}
uint32_t sd_read(int ren) {
if (ren) {
uint32_t data;
fread(&data, 4, 1, fp);
//printf("read data = 0x%08x\n", *data);
return data;
}
return 0xdeadbeaf;
}
void init_sd(void) {
fp = fopen("/home/xyn/debian/debian.img", "r");
if(!fp) {
printf("[warning] sdcard img not found\n");
}
}
src/test/vcs/uart.c 已删除 100644 → 0
浏览文件 @ 22deac3a
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
void uart_putchar(char c)
{
printf("%c", c);
fflush(stdout);
}
\ No newline at end of file
src/test/vcs/xs_vcs_top.v 已删除 100644 → 0
浏览文件 @ 22deac3a
module xs_system_top();
wire clock;
wire reset;
wire [63:0] io_difftest_r_0;
wire [63:0] io_difftest_r_1;
wire [63:0] io_difftest_r_2;
wire [63:0] io_difftest_r_3;
wire [63:0] io_difftest_r_4;
wire [63:0] io_difftest_r_5;
wire [63:0] io_difftest_r_6;
wire [63:0] io_difftest_r_7;
wire [63:0] io_difftest_r_8;
wire [63:0] io_difftest_r_9;
wire [63:0] io_difftest_r_10;
wire [63:0] io_difftest_r_11;
wire [63:0] io_difftest_r_12;
wire [63:0] io_difftest_r_13;
wire [63:0] io_difftest_r_14;
wire [63:0] io_difftest_r_15;
wire [63:0] io_difftest_r_16;
wire [63:0] io_difftest_r_17;
wire [63:0] io_difftest_r_18;
wire [63:0] io_difftest_r_19;
wire [63:0] io_difftest_r_20;
wire [63:0] io_difftest_r_21;
wire [63:0] io_difftest_r_22;
wire [63:0] io_difftest_r_23;
wire [63:0] io_difftest_r_24;
wire [63:0] io_difftest_r_25;
wire [63:0] io_difftest_r_26;
wire [63:0] io_difftest_r_27;
wire [63:0] io_difftest_r_28;
wire [63:0] io_difftest_r_29;
wire [63:0] io_difftest_r_30;
wire [63:0] io_difftest_r_31;
wire [63:0] io_difftest_r_32;
wire [63:0] io_difftest_r_33;
wire [63:0] io_difftest_r_34;
wire [63:0] io_difftest_r_35;
wire [63:0] io_difftest_r_36;
wire [63:0] io_difftest_r_37;
wire [63:0] io_difftest_r_38;
wire [63:0] io_difftest_r_39;
wire [63:0] io_difftest_r_40;
wire [63:0] io_difftest_r_41;
wire [63:0] io_difftest_r_42;
wire [63:0] io_difftest_r_43;
wire [63:0] io_difftest_r_44;
wire [63:0] io_difftest_r_45;
wire [63:0] io_difftest_r_46;
wire [63:0] io_difftest_r_47;
wire [63:0] io_difftest_r_48;
wire [63:0] io_difftest_r_49;
wire [63:0] io_difftest_r_50;
wire [63:0] io_difftest_r_51;
wire [63:0] io_difftest_r_52;
wire [63:0] io_difftest_r_53;
wire [63:0] io_difftest_r_54;
wire [63:0] io_difftest_r_55;
wire [63:0] io_difftest_r_56;
wire [63:0] io_difftest_r_57;
wire [63:0] io_difftest_r_58;
wire [63:0] io_difftest_r_59;
wire [63:0] io_difftest_r_60;
wire [63:0] io_difftest_r_61;
wire [63:0] io_difftest_r_62;
wire [63:0] io_difftest_r_63;
wire [31:0] io_difftest_commit;
wire [63:0] io_difftest_thisPC;
wire [31:0] io_difftest_thisINST;
wire [31:0] io_difftest_skip;
wire [31:0] io_difftest_wen;
wire [63:0] io_difftest_wdata_0;
wire [63:0] io_difftest_wdata_1;
wire [63:0] io_difftest_wdata_2;
wire [63:0] io_difftest_wdata_3;
wire [63:0] io_difftest_wdata_4;
wire [63:0] io_difftest_wdata_5;
wire [31:0] io_difftest_wdst_0;
wire [31:0] io_difftest_wdst_1;
wire [31:0] io_difftest_wdst_2;
wire [31:0] io_difftest_wdst_3;
wire [31:0] io_difftest_wdst_4;
wire [31:0] io_difftest_wdst_5;
wire [63:0] io_difftest_wpc_0;
wire [63:0] io_difftest_wpc_1;
wire [63:0] io_difftest_wpc_2;
wire [63:0] io_difftest_wpc_3;
wire [63:0] io_difftest_wpc_4;
wire [63:0] io_difftest_wpc_5;
wire [31:0] io_difftest_isRVC;
wire [63:0] io_difftest_intrNO;
wire [63:0] io_difftest_cause;
wire [1:0] io_difftest_priviledgeMode;
wire [63:0] io_difftest_mstatus;
wire [63:0] io_difftest_sstatus;
wire [63:0] io_difftest_mepc;
wire [63:0] io_difftest_sepc;
wire [63:0] io_difftest_mtval;
wire [63:0] io_difftest_stval;
wire [63:0] io_difftest_mtvec;
wire [63:0] io_difftest_stvec;
wire [63:0] io_difftest_mcause;
wire [63:0] io_difftest_scause;
wire [63:0] io_difftest_satp;
wire [63:0] io_difftest_mip;
wire [63:0] io_difftest_mie;
wire [63:0] io_difftest_mscratch;
wire [63:0] io_difftest_sscratch;
wire [63:0] io_difftest_mideleg;
wire [63:0] io_difftest_medeleg;
wire io_difftest_scFailed;
wire [1:0] io_difftest_storeCommit;
wire [63:0] io_difftest_storeAddr_0;
wire [63:0] io_difftest_storeAddr_1;
wire [63:0] io_difftest_storeData_0;
wire [63:0] io_difftest_storeData_1;
wire [7:0] io_difftest_storeMask_0;
wire [7:0] io_difftest_storeMask_1;
wire io_difftest_sbufferResp;
wire [63:0] io_difftest_sbufferAddr;
wire [7:0] io_difftest_sbufferData_0;
wire [7:0] io_difftest_sbufferData_1;
wire [7:0] io_difftest_sbufferData_2;
wire [7:0] io_difftest_sbufferData_3;
wire [7:0] io_difftest_sbufferData_4;
wire [7:0] io_difftest_sbufferData_5;
wire [7:0] io_difftest_sbufferData_6;
wire [7:0] io_difftest_sbufferData_7;
wire [7:0] io_difftest_sbufferData_8;
wire [7:0] io_difftest_sbufferData_9;
wire [7:0] io_difftest_sbufferData_10;
wire [7:0] io_difftest_sbufferData_11;
wire [7:0] io_difftest_sbufferData_12;
wire [7:0] io_difftest_sbufferData_13;
wire [7:0] io_difftest_sbufferData_14;
wire [7:0] io_difftest_sbufferData_15;
wire [7:0] io_difftest_sbufferData_16;
wire [7:0] io_difftest_sbufferData_17;
wire [7:0] io_difftest_sbufferData_18;
wire [7:0] io_difftest_sbufferData_19;
wire [7:0] io_difftest_sbufferData_20;
wire [7:0] io_difftest_sbufferData_21;
wire [7:0] io_difftest_sbufferData_22;
wire [7:0] io_difftest_sbufferData_23;
wire [7:0] io_difftest_sbufferData_24;
wire [7:0] io_difftest_sbufferData_25;
wire [7:0] io_difftest_sbufferData_26;
wire [7:0] io_difftest_sbufferData_27;
wire [7:0] io_difftest_sbufferData_28;
wire [7:0] io_difftest_sbufferData_29;
wire [7:0] io_difftest_sbufferData_30;
wire [7:0] io_difftest_sbufferData_31;
wire [7:0] io_difftest_sbufferData_32;
wire [7:0] io_difftest_sbufferData_33;
wire [7:0] io_difftest_sbufferData_34;
wire [7:0] io_difftest_sbufferData_35;
wire [7:0] io_difftest_sbufferData_36;
wire [7:0] io_difftest_sbufferData_37;
wire [7:0] io_difftest_sbufferData_38;
wire [7:0] io_difftest_sbufferData_39;
wire [7:0] io_difftest_sbufferData_40;
wire [7:0] io_difftest_sbufferData_41;
wire [7:0] io_difftest_sbufferData_42;
wire [7:0] io_difftest_sbufferData_43;
wire [7:0] io_difftest_sbufferData_44;
wire [7:0] io_difftest_sbufferData_45;
wire [7:0] io_difftest_sbufferData_46;
wire [7:0] io_difftest_sbufferData_47;
wire [7:0] io_difftest_sbufferData_48;
wire [7:0] io_difftest_sbufferData_49;
wire [7:0] io_difftest_sbufferData_50;
wire [7:0] io_difftest_sbufferData_51;
wire [7:0] io_difftest_sbufferData_52;
wire [7:0] io_difftest_sbufferData_53;
wire [7:0] io_difftest_sbufferData_54;
wire [7:0] io_difftest_sbufferData_55;
wire [7:0] io_difftest_sbufferData_56;
wire [7:0] io_difftest_sbufferData_57;
wire [7:0] io_difftest_sbufferData_58;
wire [7:0] io_difftest_sbufferData_59;
wire [7:0] io_difftest_sbufferData_60;
wire [7:0] io_difftest_sbufferData_61;
wire [7:0] io_difftest_sbufferData_62;
wire [7:0] io_difftest_sbufferData_63;
wire [63:0] io_difftest_sbufferMask;
wire [63:0] io_logCtrl_log_begin;
wire [63:0] io_logCtrl_log_end;
wire [63:0] io_logCtrl_log_level;
wire io_trap_valid;
wire [2:0] io_trap_code;
wire [38:0] io_trap_pc;
wire [63:0] io_trap_cycleCnt;
wire [63:0] io_trap_instrCnt;
wire io_uart_out_valid;
wire [7:0] io_uart_out_ch;
wire io_uart_in_valid;
wire [7:0] io_uart_in_ch;
assign io_logCtrl_log_begin = 'h0;
assign io_logCtrl_log_end = 'h0;
assign io_logCtrl_log_level = 'h0;
rcg rcg0
(
.clock(clock),
.reset(reset)
);
UARTHelper UARTHelper0
(
.clock(clock),
.reset(reset),
.putchar_valid(io_uart_out_valid),
.putchar_ch(io_uart_out_ch),
.getchar_valid(io_uart_in_valid),
.getchar_ch(io_uart_in_ch)
);
XSSimSoC XSSimSoC0
(
.clock(clock),
.reset(reset),
.io_difftest_r_0(io_difftest_r_0),
.io_difftest_r_1(io_difftest_r_1),
.io_difftest_r_2(io_difftest_r_2),
.io_difftest_r_3(io_difftest_r_3),
.io_difftest_r_4(io_difftest_r_4),
.io_difftest_r_5(io_difftest_r_5),
.io_difftest_r_6(io_difftest_r_6),
.io_difftest_r_7(io_difftest_r_7),
.io_difftest_r_8(io_difftest_r_8),
.io_difftest_r_9(io_difftest_r_9),
.io_difftest_r_10(io_difftest_r_10),
.io_difftest_r_11(io_difftest_r_11),
.io_difftest_r_12(io_difftest_r_12),
.io_difftest_r_13(io_difftest_r_13),
.io_difftest_r_14(io_difftest_r_14),
.io_difftest_r_15(io_difftest_r_15),
.io_difftest_r_16(io_difftest_r_16),
.io_difftest_r_17(io_difftest_r_17),
.io_difftest_r_18(io_difftest_r_18),
.io_difftest_r_19(io_difftest_r_19),
.io_difftest_r_20(io_difftest_r_20),
.io_difftest_r_21(io_difftest_r_21),
.io_difftest_r_22(io_difftest_r_22),
.io_difftest_r_23(io_difftest_r_23),
.io_difftest_r_24(io_difftest_r_24),
.io_difftest_r_25(io_difftest_r_25),
.io_difftest_r_26(io_difftest_r_26),
.io_difftest_r_27(io_difftest_r_27),
.io_difftest_r_28(io_difftest_r_28),
.io_difftest_r_29(io_difftest_r_29),
.io_difftest_r_30(io_difftest_r_30),
.io_difftest_r_31(io_difftest_r_31),
.io_difftest_r_32(io_difftest_r_32),
.io_difftest_r_33(io_difftest_r_33),
.io_difftest_r_34(io_difftest_r_34),
.io_difftest_r_35(io_difftest_r_35),
.io_difftest_r_36(io_difftest_r_36),
.io_difftest_r_37(io_difftest_r_37),
.io_difftest_r_38(io_difftest_r_38),
.io_difftest_r_39(io_difftest_r_39),
.io_difftest_r_40(io_difftest_r_40),
.io_difftest_r_41(io_difftest_r_41),
.io_difftest_r_42(io_difftest_r_42),
.io_difftest_r_43(io_difftest_r_43),
.io_difftest_r_44(io_difftest_r_44),
.io_difftest_r_45(io_difftest_r_45),
.io_difftest_r_46(io_difftest_r_46),
.io_difftest_r_47(io_difftest_r_47),
.io_difftest_r_48(io_difftest_r_48),
.io_difftest_r_49(io_difftest_r_49),
.io_difftest_r_50(io_difftest_r_50),
.io_difftest_r_51(io_difftest_r_51),
.io_difftest_r_52(io_difftest_r_52),
.io_difftest_r_53(io_difftest_r_53),
.io_difftest_r_54(io_difftest_r_54),
.io_difftest_r_55(io_difftest_r_55),
.io_difftest_r_56(io_difftest_r_56),
.io_difftest_r_57(io_difftest_r_57),
.io_difftest_r_58(io_difftest_r_58),
.io_difftest_r_59(io_difftest_r_59),
.io_difftest_r_60(io_difftest_r_60),
.io_difftest_r_61(io_difftest_r_61),
.io_difftest_r_62(io_difftest_r_62),
.io_difftest_r_63(io_difftest_r_63),
.io_difftest_commit(io_difftest_commit),
.io_difftest_thisPC(io_difftest_thisPC),
.io_difftest_thisINST(io_difftest_thisINST),
.io_difftest_skip(io_difftest_skip),
.io_difftest_wen(io_difftest_wen),
.io_difftest_wdata_0(io_difftest_wdata_0),
.io_difftest_wdata_1(io_difftest_wdata_1),
.io_difftest_wdata_2(io_difftest_wdata_2),
.io_difftest_wdata_3(io_difftest_wdata_3),
.io_difftest_wdata_4(io_difftest_wdata_4),
.io_difftest_wdata_5(io_difftest_wdata_5),
.io_difftest_wdst_0(io_difftest_wdst_0),
.io_difftest_wdst_1(io_difftest_wdst_1),
.io_difftest_wdst_2(io_difftest_wdst_2),
.io_difftest_wdst_3(io_difftest_wdst_3),
.io_difftest_wdst_4(io_difftest_wdst_4),
.io_difftest_wdst_5(io_difftest_wdst_5),
.io_difftest_wpc_0(io_difftest_wpc_0),
.io_difftest_wpc_1(io_difftest_wpc_1),
.io_difftest_wpc_2(io_difftest_wpc_2),
.io_difftest_wpc_3(io_difftest_wpc_3),
.io_difftest_wpc_4(io_difftest_wpc_4),
.io_difftest_wpc_5(io_difftest_wpc_5),
.io_difftest_isRVC(io_difftest_isRVC),
.io_difftest_intrNO(io_difftest_intrNO),
.io_difftest_cause(io_difftest_cause),
.io_difftest_priviledgeMode(io_difftest_priviledgeMode),
.io_difftest_mstatus(io_difftest_mstatus),
.io_difftest_sstatus(io_difftest_sstatus),
.io_difftest_mepc(io_difftest_mepc),
.io_difftest_sepc(io_difftest_sepc),
.io_difftest_mtval(io_difftest_mtval),
.io_difftest_stval(io_difftest_stval),
.io_difftest_mtvec(io_difftest_mtvec),
.io_difftest_stvec(io_difftest_stvec),
.io_difftest_mcause(io_difftest_mcause),
.io_difftest_scause(io_difftest_scause),
.io_difftest_satp(io_difftest_satp),
.io_difftest_mip(io_difftest_mip),
.io_difftest_mie(io_difftest_mie),
.io_difftest_mscratch(io_difftest_mscratch),
.io_difftest_sscratch(io_difftest_sscratch),
.io_difftest_mideleg(io_difftest_mideleg),
.io_difftest_medeleg(io_difftest_medeleg),
.io_difftest_scFailed(io_difftest_scFailed),
.io_difftest_storeCommit(io_difftest_storeCommit),
.io_difftest_storeAddr_0(io_difftest_storeAddr_0),
.io_difftest_storeAddr_1(io_difftest_storeAddr_1),
.io_difftest_storeData_0(io_difftest_storeData_0),
.io_difftest_storeData_1(io_difftest_storeData_1),
.io_difftest_storeMask_0(io_difftest_storeMask_0),
.io_difftest_storeMask_1(io_difftest_storeMask_1),
.io_difftest_sbufferResp(io_difftest_sbufferResp),
.io_difftest_sbufferAddr(io_difftest_sbufferAddr),
.io_difftest_sbufferData_0(io_difftest_sbufferData_0),
.io_difftest_sbufferData_1(io_difftest_sbufferData_1),
.io_difftest_sbufferData_2(io_difftest_sbufferData_2),
.io_difftest_sbufferData_3(io_difftest_sbufferData_3),
.io_difftest_sbufferData_4(io_difftest_sbufferData_4),
.io_difftest_sbufferData_5(io_difftest_sbufferData_5),
.io_difftest_sbufferData_6(io_difftest_sbufferData_6),
.io_difftest_sbufferData_7(io_difftest_sbufferData_7),
.io_difftest_sbufferData_8(io_difftest_sbufferData_8),
.io_difftest_sbufferData_9(io_difftest_sbufferData_9),
.io_difftest_sbufferData_10(io_difftest_sbufferData_10),
.io_difftest_sbufferData_11(io_difftest_sbufferData_11),
.io_difftest_sbufferData_12(io_difftest_sbufferData_12),
.io_difftest_sbufferData_13(io_difftest_sbufferData_13),
.io_difftest_sbufferData_14(io_difftest_sbufferData_14),
.io_difftest_sbufferData_15(io_difftest_sbufferData_15),
.io_difftest_sbufferData_16(io_difftest_sbufferData_16),
.io_difftest_sbufferData_17(io_difftest_sbufferData_17),
.io_difftest_sbufferData_18(io_difftest_sbufferData_18),
.io_difftest_sbufferData_19(io_difftest_sbufferData_19),
.io_difftest_sbufferData_20(io_difftest_sbufferData_20),
.io_difftest_sbufferData_21(io_difftest_sbufferData_21),
.io_difftest_sbufferData_22(io_difftest_sbufferData_22),
.io_difftest_sbufferData_23(io_difftest_sbufferData_23),
.io_difftest_sbufferData_24(io_difftest_sbufferData_24),
.io_difftest_sbufferData_25(io_difftest_sbufferData_25),
.io_difftest_sbufferData_26(io_difftest_sbufferData_26),
.io_difftest_sbufferData_27(io_difftest_sbufferData_27),
.io_difftest_sbufferData_28(io_difftest_sbufferData_28),
.io_difftest_sbufferData_29(io_difftest_sbufferData_29),
.io_difftest_sbufferData_30(io_difftest_sbufferData_30),
.io_difftest_sbufferData_31(io_difftest_sbufferData_31),
.io_difftest_sbufferData_32(io_difftest_sbufferData_32),
.io_difftest_sbufferData_33(io_difftest_sbufferData_33),
.io_difftest_sbufferData_34(io_difftest_sbufferData_34),
.io_difftest_sbufferData_35(io_difftest_sbufferData_35),
.io_difftest_sbufferData_36(io_difftest_sbufferData_36),
.io_difftest_sbufferData_37(io_difftest_sbufferData_37),
.io_difftest_sbufferData_38(io_difftest_sbufferData_38),
.io_difftest_sbufferData_39(io_difftest_sbufferData_39),
.io_difftest_sbufferData_40(io_difftest_sbufferData_40),
.io_difftest_sbufferData_41(io_difftest_sbufferData_41),
.io_difftest_sbufferData_42(io_difftest_sbufferData_42),
.io_difftest_sbufferData_43(io_difftest_sbufferData_43),
.io_difftest_sbufferData_44(io_difftest_sbufferData_44),
.io_difftest_sbufferData_45(io_difftest_sbufferData_45),
.io_difftest_sbufferData_46(io_difftest_sbufferData_46),
.io_difftest_sbufferData_47(io_difftest_sbufferData_47),
.io_difftest_sbufferData_48(io_difftest_sbufferData_48),
.io_difftest_sbufferData_49(io_difftest_sbufferData_49),
.io_difftest_sbufferData_50(io_difftest_sbufferData_50),
.io_difftest_sbufferData_51(io_difftest_sbufferData_51),
.io_difftest_sbufferData_52(io_difftest_sbufferData_52),
.io_difftest_sbufferData_53(io_difftest_sbufferData_53),
.io_difftest_sbufferData_54(io_difftest_sbufferData_54),
.io_difftest_sbufferData_55(io_difftest_sbufferData_55),
.io_difftest_sbufferData_56(io_difftest_sbufferData_56),
.io_difftest_sbufferData_57(io_difftest_sbufferData_57),
.io_difftest_sbufferData_58(io_difftest_sbufferData_58),
.io_difftest_sbufferData_59(io_difftest_sbufferData_59),
.io_difftest_sbufferData_60(io_difftest_sbufferData_60),
.io_difftest_sbufferData_61(io_difftest_sbufferData_61),
.io_difftest_sbufferData_62(io_difftest_sbufferData_62),
.io_difftest_sbufferData_63(io_difftest_sbufferData_63),
.io_difftest_sbufferMask(io_difftest_sbufferMask),
.io_logCtrl_log_begin(io_logCtrl_log_begin),
.io_logCtrl_log_end(io_logCtrl_log_end),
.io_logCtrl_log_level(io_logCtrl_log_level),
.io_trap_valid(io_trap_valid),
.io_trap_code(io_trap_code),
.io_trap_pc(io_trap_pc),
.io_trap_cycleCnt(io_trap_cycleCnt),
.io_trap_instrCnt(io_trap_instrCnt),
.io_uart_out_valid(io_uart_out_valid),
.io_uart_out_ch(io_uart_out_ch),
.io_uart_in_valid(io_uart_in_valid),
.io_uart_in_ch(io_uart_in_ch)
);
endmodule
module rcg
(
clock,
reset
);
output clock;
output reset;
reg clock;
reg reset;
initial begin
clock <= 0;
reset <= 1;
#500 reset <= 0;
end
always begin
#1 clock <= ~clock;
end
initial begin
$vcdpluson;
end
endmodule
src/test/vsrc/assert.v 已删除 100644 → 0
浏览文件 @ 22deac3a
import "DPI-C" function void xs_assert
(
input longint line
);
src/test/vsrc/difftest.v → src/test/vsrc/common/difftest.v
浏览文件 @ acd0ebb7
......@@ -569,6 +569,6 @@ endmodule
input [63:0] ptwData_3
);
`DIFFTEST_MOD_DPIC_CALL_BEGIN_WITH_EN(ptwResp, PtwEvent) (
coreid, ptwResp, ptwData_0, ptwData_1, ptwData_2, ptwData_3
coreid, ptwResp, ptwAddr, ptwData_0, ptwData_1, ptwData_2, ptwData_3
) `DIFFTEST_MOD_DPIC_CALL_END_WITH_EN(PtwEvent)
endmodule
src/test/vsrc/vcs/top.v 0 → 100644
浏览文件 @ acd0ebb7
import "DPI-C" function void simv_init();
import "DPI-C" function void simv_step();
module tb_top();
reg clock;
reg reset;
wire [63:0] io_logCtrl_log_begin;
wire [63:0] io_logCtrl_log_end;
wire [63:0] io_logCtrl_log_level;
wire io_perfInfo_clean;
wire io_perfInfo_dump;
wire io_uart_out_valid;
wire [ 7:0] io_uart_out_ch;
wire io_uart_in_valid;
wire [ 7:0] io_uart_in_ch;
initial begin
clock = 0;
reset = 1;
#100 reset = 0;
if ($test$plusargs("dump-wave")) begin
$vcdplusfile("simv.vpd");
$vcdpluson;
end
end
always #1 clock <= ~clock;
SimTop sim(
.clock(clock),
.reset(reset),
.io_logCtrl_log_begin(io_logCtrl_log_begin),
.io_logCtrl_log_end(io_logCtrl_log_end),
.io_logCtrl_log_level(io_logCtrl_log_level),
.io_perfInfo_clean(io_perfInfo_clean),
.io_perfInfo_dump(io_perfInfo_dump),
.io_uart_out_valid(io_uart_out_valid),
.io_uart_out_ch(io_uart_out_ch),
.io_uart_in_valid(io_uart_in_valid),
.io_uart_in_ch(io_uart_in_ch)
);
assign io_logCtrl_log_begin = 0;
assign io_logCtrl_log_end = 0;
assign io_logCtrl_log_level = 0;
assign io_perfInfo_clean = 0;
assign io_perfInfo_dump = 0;
assign io_uart_in_ch = 8'hff;
always @(posedge clock) begin
if (!reset && io_uart_out_valid) begin
$write("%c", io_uart_out_ch);
end
end
reg has_init;
always @(posedge clock) begin
if (reset) begin
has_init <= 1'b0;
end
else if (!has_init) begin
simv_init();
has_init <= 1'b1;
end
if (!reset && has_init) begin
simv_step();
end
end
endmodule
vcs.mk 0 → 100644
浏览文件 @ acd0ebb7
VCS_TARGET = simv
VCS_CSRC_DIR = $(abspath ./src/test/csrc/vcs)
VCS_CXXFILES = $(SIM_CXXFILES) $(DIFFTEST_CXXFILES) $(shell find $(VCS_CSRC_DIR) -name "*.cpp")
VCS_CXXFLAGS += -std=c++11 -static -Wall -I$(VCS_CSRC_DIR) -I$(SIM_CSRC_DIR) -I$(DIFFTEST_CSRC_DIR)
VCS_LDFLAGS += -lpthread -lSDL2 -ldl -lz
VCS_VSRC_DIR = $(abspath ./src/test/vsrc/vcs)
VCS_VFILES = $(SIM_VSRC) $(shell find $(VCS_VSRC_DIR) -name "*.v")
VCS_SEARCH_DIR = $(abspath ./build)
VCS_BUILD_DIR = $(abspath ./build/simv-compile)
VCS_FLAGS += -full64 +v2k -timescale=1ns/1ns -sverilog -debug_access+all +lint=TFIPC-L
# randomize all undefined signals (instead of using X)
VCS_FLAGS += +define+RANDOMIZE_GARBAGE_ASSIGN +define+RANDOMIZE_INVALID_ASSIGN
VCS_FLAGS += +define+RANDOMIZE_MEM_INIT +define+RANDOMIZE_DELAY=0 +define+RANDOMIZE_REG_INIT
# SRAM lib defines
VCS_FLAGS += +define+UNIT_DELAY +define+no_warning
# C++ flags
VCS_FLAGS += -CFLAGS "$(VCS_CXXFLAGS)" -LDFLAGS "$(VCS_LDFLAGS)"
# search build for other missing verilog files
VCS_FLAGS += -y $(VCS_SEARCH_DIR) +libext+.v
# build files put into $(VCS_BUILD_DIR)
VCS_FLAGS += -Mdir=$(VCS_BUILD_DIR)
$(VCS_TARGET): $(SIM_TOP_V) $(VCS_CXXFILES) $(VCS_VFILES)
vcs $(VCS_FLAGS) $(SIM_TOP_V) $(VCS_CXXFILES) $(VCS_VFILES)
vcs-clean:
rm -rf simv csrc DVEfiles simv.daidir stack.info.* ucli.key $(VCS_BUILD_DIR)
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