- 05 3月, 2021 1 次提交
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由 Lemover 提交于
* RS: optimize numExist signal * RS: fix some typo * RS: optimize deq logic for block-nonfeedback rs
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- 04 3月, 2021 5 次提交
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由 ljw 提交于
* NewSbuffer: allow multi-inflight dcache request to improve performance * NewSbuffer: fix bugs in replace && add more debug print * SbufferTest: update sbuffer test
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由 Jay 提交于
* Replacement: change state in way method. * State change is also needed when miss occurs, otherwise we will choose a way that has been just refilled into cache as the victim. * Optimize ctrlblock timing (#620) * CtrlBlock: delay exception flush for 1 cycle * CtrlBlock: delay load replay for 1 cycle * roq: delay wb from exu for one clock cycle to meet timing * CtrlBlock: fix pipeline bug between decode and rename Co-authored-by: NYinan Xu <xuyinan1997@gmail.com> * L1plusCache: use plru replacement policy. * ICache: fix mmio bugs 1. MMIO cut helper uses packet align logic 2. still send req to uncache when flush * ICache: change packet from mmio use packet align as the mem * IntrUncache: fix state bug state will change into s_invalid and get stuck * fix Registers that not being initiated
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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由 ljw 提交于
* Ftq: save 'hist' in regs * Ftq: save 'br_mask' in regs
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- 03 3月, 2021 9 次提交
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由 zhanglinjuan 提交于
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由 ljw 提交于
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由 Lingrui98 提交于
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由 zfw 提交于
* sbuffer: use plru * sbuffer: use drainIdx when drain sbuffer * Fix typo * sbuffer: set the evict threshold=12 Co-authored-by: Nljw <linjiav@outlook.com>
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由 Steve Gou 提交于
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由 Steve Gou 提交于
* core: enable sc * sc: calculate sum again on update * sc: clean ups * sc: add some debug info * sc, tage, bim: fix wrbypass logic, add wrbypass for SC * core: disable sc by default Co-authored-by: Njinyue110 <jinyue161@mails.ucas.ac.cn>
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
We pass redirect ghist directly to a mux, whose output is connected to bpu.s1_hist, so that the delay of three cascaded 64-bit-wide 2-1 mux could be saved
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- 02 3月, 2021 2 次提交
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由 ljw 提交于
* CtrlBlock: delay exception flush for 1 cycle * CtrlBlock: delay load replay for 1 cycle * roq: delay wb from exu for one clock cycle to meet timing * CtrlBlock: fix pipeline bug between decode and rename Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>
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由 Steve Gou 提交于
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- 01 3月, 2021 3 次提交
- 28 2月, 2021 15 次提交
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由 Lemover 提交于
* TLB: add more tlb and ptw's perf counter * TLB: change perf count signal name(rm module name)
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由 jinyue110 提交于
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由 ljw 提交于
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由 Yinan Xu 提交于
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由 ljw 提交于
* Ftq: use reg instead 4r_sram * Ftq: use delayed value form exu output
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 jinyue110 提交于
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由 zoujr 提交于
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由 zoujr 提交于
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由 wakafa 提交于
* perf: set acc arg of XSPerf as false by default * perf: add write-port competition counter for intBlock & floatBlock * perf: remove prefix of perf signal * perf: add perf-cnt for interface between frontend & backend * perf: modify perf-cnt for prefetchers
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由 ljw 提交于
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由 William Wang 提交于
* WaitTable: add waittable framework * WaitTable: get replay info from RedirectGenerator * StoreQueue: maintain issuePtr for load rs * RS: add loadWait to rs (only for load Unit's rs) * WaitTable: fix update logic * StoreQueue: fix issuePtr update logic * chore: set loadWaitBit in ibuffer * StoreQueue: fix issuePtrExt update logic Former logic does not work well with mmio logic We may also make sure that issuePtrExt is not before cmtPtrExt * WaitTable: write with priority * StoreQueue: fix issuePtrExt update logic for mmio * chore: fix typos * CSR: add slvpredctrl * slvpredctrl will control load violation predict micro architecture * WaitTable: use xor folded pc to index waittable Co-authored-by: NZhangZifei <1773908404@qq.com>
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由 Steve Gou 提交于
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由 zoujr 提交于
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- 27 2月, 2021 5 次提交
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由 Yinan Xu 提交于
* intWb: set wb.valid when !fpwen to allow writeback if !fpwen and !rfwen * rs: fix replay delay to avoid deadlock * load: fix tlb feedback
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由 zoujr 提交于
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由 Lemover 提交于
* RS: pass ExuConfigs instead of wake-up port number to rs * RS: store's rs's base-src dont care fp wake-up
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由 Yinan Xu 提交于
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由 Lemover 提交于
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