dispatch2: optimize load/store busyTable read timing and fuType, srcState usages

* however, some codes are dirty requiring refactor

* should be compatible with single core difftest framework

fix pipeline flush bug

dispatch,MemBlock: optimize fuType usages

Trace debug

div: don't accept new request when it's cancelled

SRAMTemplate: fix wmask and update license

LoadQueue: fix lq writeback uop read logic

L2, L3: change SRAM width to 256 bit.

* now "--fpga-platform --dualcore" will be reserved for dualcore without
difftest

dev-prefetcher: replace stream prefetch with best-offset in L2Prefetcher

Give replay check an extra cycle (store s3)