dispatch1: fix commitType

src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala

@@ -70,7 +70,7 @@ class Dispatch1 extends XSModule with HasExceptionNO {
   val updatedOldPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W)))
 
   for (i <- 0 until RenameWidth) {
-    updatedCommitType(i) := Cat(isLs(i), isStore(i) | isBranch(i))
+    updatedCommitType(i) := Cat(isLs(i), (isStore(i) && !isAMO(i)) | isBranch(i))
     updatedPsrc1(i) := io.fromRename.take(i).map(_.bits.pdest)
       .zip(if (i == 0) Seq() else io.renameBypass.lsrc1_bypass(i-1).asBools)
       .foldLeft(io.fromRename(i).bits.psrc1) {

src/main/scala/xiangshan/package.scala

@@ -54,7 +54,7 @@ package object xiangshan {
     def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U
     def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1)
     def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0)
-    def isAMO(fuType: UInt) = isMemExu(fuType) && fuType(1)
+    def isAMO(fuType: UInt) = fuType(1)
 
     def jmpCanAccept(fuType: UInt) = !fuType(2)
     def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1)