* add a shift state to improve timing
  * shifting on the intermeidate result costs a lot

TODO:
* Injecting interrupts in decode stage with NOP.
* Save mstatus.mie to mstatus.mpie

* change the fix clk to 40MHz to obtain good timing result
  * 50MHz and the 27MHz i2c clock yield bad timing result for inter-clock

This reverts commit e2e2e3f1.

* For VGA, the original wmask seems correct. But now UART does not work.

* only support write

* Should assert req.ready once it is accepted by the slave. The master
  should guarantee only one request is in-flight.

* Due to the modification of AXI4Slave, now AXI4RAM has 2 cycle of
  latency.
* The display is still not perfect. Some vertical lines are still wrong.
* We should modify the vga code to be independent of the behavior of
  AXI4RAM.

* BTB should also be flushed when executing fence.i
* Now we can let the init program load PAL to run.

* When executing fence.i, the pipeline and ICache will be flushed. New
  instructions will be fetched from memory, or DCache with coherence
  support.
* With fence.i, we should pass nexus-am/tests/cachetest/test/loader.c.

This reverts commit 7c95c717.

* The original bug is caused by 32-bit width of CacheProbeStage, which
  is merged after rv64 and forget to change the width to 64-bit.