utils,RegMap: support different raddr and waddr for AXI4

src/main/scala/utils/RegMap.scala

@@ -5,12 +5,14 @@ import chisel3.util._
 
 object RegMap {
   def apply(addr: Int, reg: UInt, wfn: UInt => UInt = (x => x)) = (addr, (reg, wfn))
-  def generate(mapping: Map[Int, (UInt, UInt => UInt)], addr: UInt, rdata: UInt,
-    wen: Bool, wdata: UInt, wmask: UInt) = {
+  def generate(mapping: Map[Int, (UInt, UInt => UInt)], raddr: UInt, rdata: UInt,
+    waddr: UInt, wen: Bool, wdata: UInt, wmask: UInt):Unit = {
     val chiselMapping = mapping.map { case (a, (r, w)) => (a.U, r, w) }
-    rdata := LookupTree(addr, chiselMapping.map { case (a, r, w) => (a, r) })
+    rdata := LookupTree(raddr, chiselMapping.map { case (a, r, w) => (a, r) })
     when (wen) {
-      chiselMapping.map { case (a, r, w) => when (addr === a) { r := w(MaskData(r, wdata, wmask)) } }
+      chiselMapping.map { case (a, r, w) => when (waddr === a) { r := w(MaskData(r, wdata, wmask)) } }
     }
   }
+  def generate(mapping: Map[Int, (UInt, UInt => UInt)], addr: UInt, rdata: UInt,
+    wen: Bool, wdata: UInt, wmask: UInt):Unit = generate(mapping, addr, rdata, addr, wen, wdata, wmask)
 }