XSInfo(io.commits(i).valid&&shouldWalkVec(i),"walked pc %x wen %d ldst %d data %x\n",microOp(ringBufferTail+i.U).cf.pc,microOp(ringBufferTail+i.U).ctrl.rfWen,microOp(ringBufferTail+i.U).ctrl.ldest,exuData(ringBufferTail+i.U))
XSInfo(io.commits(i).valid&&shouldWalkVec(i),"walked pc %x wen %d ldst %d data %x\n",
microOp(ringBufferWalk-i.U).cf.pc,
microOp(ringBufferWalk-i.U).ctrl.rfWen,
microOp(ringBufferWalk-i.U).ctrl.ldest,
exuData(ringBufferWalk-i.U)
)
}
io.commits(i).bits.isWalk:=state===s_walk
}
...
...
@@ -125,7 +133,7 @@ class Roq(implicit val p: XSConfig) extends XSModule {