pipeline: fixing bugs in "dummy" test

src/main/scala/xiangshan/backend/Backend.scala

@@ -135,6 +135,7 @@ class Backend(implicit val p: XSConfig) extends XSModule
     rfWrite
   }
 
+  //FIXME: only write back when "wen"
   intWbArb.io.in <> wbIntReqs
   intRf.io.writePorts <> wbIntResults.map(exuOutToRfWrite)
 

src/main/scala/xiangshan/backend/exu/Lsu.scala

@@ -144,16 +144,9 @@ class Lsu extends Exu(
       LSUOpType.lwu  -> ZeroExt(rdataSel(31, 0), XLEN)
   ))
 
-  io.in.ready := io.out.fire()
-
-  io.out.valid := !retiringStore && (Mux(partialLoad, state === s_partialLoad, dmem.resp.fire() && (state === s_wait_resp)) || isStoreIn)
-  io.out.bits.uop <> io.in.bits.uop
-  io.out.bits.data := Mux(partialLoad, rdataPartialLoad, rdata)
-  // io.out.bits.debug.isMMIO := AddressSpace.isMMIO(addr) && io.out.valid
-  io.out.bits.debug.isMMIO := AddressSpace.isMMIO(addr) //for debug
 
   // if store, add it to store queue
-  val stqEnqueue = valid && isStore && !stqFull
+  val stqEnqueue = validIn && isStoreIn && !stqFull
   when(stqEnqueue){
     stqPtr(stqHead) := emptySlot
     stqData(emptySlot).src1 := src1In
@@ -174,8 +167,29 @@ class Lsu extends Exu(
 
   // update stqTail, stqCommited
   stqCommited := stqCommited + io.scommit - stqDequeue
-  stqTail := stqTail + stqEnqueue - stqDequeue
+  stqHead := stqHead + stqEnqueue - stqDequeue
+
+  io.in.ready := io.out.fire()
+
+  io.out.valid := (!isStoreIn && !retiringStore && Mux(partialLoad, state === s_partialLoad, dmem.resp.fire() && (state === s_wait_resp)) || stqEnqueue) && io.in.valid
+  io.out.bits.uop <> io.in.bits.uop
+  io.out.bits.data := Mux(partialLoad, rdataPartialLoad, rdata)
+  // io.out.bits.debug.isMMIO := AddressSpace.isMMIO(addr) && io.out.valid
+  io.out.bits.debug.isMMIO := AddressSpace.isMMIO(addr) //for debug
+  when(io.out.fire()){
+    XSDebug("LSU fire: addr %x mmio %x isStoreIn %x retiringStore %x partialLoad %x dmem %x stqEnqueue %x state %x \n",
+      addr,
+      io.out.bits.debug.isMMIO,
+      isStoreIn,
+      retiringStore,
+      partialLoad,
+      dmem.resp.fire(),
+      stqEnqueue,
+      state
+    )
+  }
 
+  // debug
   XSDebug("state: %d (valid, ready): in (%d,%d) out (%d,%d)\n", state, io.in.valid, io.in.ready, io.out.valid, io.out.ready)
   XSDebug("stqinfo: stqValid.asUInt %b stqHead %d stqTail %d stqCommited %d emptySlot %d\n", stqValid.asUInt, stqHead, stqTail, stqCommited, emptySlot)
   XSInfo(io.dmem.req.fire() && io.dmem.req.bits.cmd =/= SimpleBusCmd.write, "[DMEM LOAD  REQ] addr 0x%x wdata 0x%x size %d\n", dmem.req.bits.addr, dmem.req.bits.wdata, dmem.req.bits.size)

src/main/scala/xiangshan/backend/issue/IssueQueue.scala

@@ -196,6 +196,7 @@ class IssueQueue(val fuTypeInt: BigInt, val wakeupCnt: Int, val bypassCnt: Int =
   // TODO: ignore ALU'cdb srcRdy, for byPass has done it
   if(wakeupCnt > 0) {
     val cdbValid = List.tabulate(wakeupCnt)(i => io.wakeUpPorts(i).valid)
+    val cdbrfWen = List.tabulate(wakeupCnt)(i => io.wakeUpPorts(i).bits.uop.ctrl.rfWen) // FIXME: handle fpWen
     val cdbData = List.tabulate(wakeupCnt)(i => io.wakeUpPorts(i).bits.data)
     val cdbPdest = List.tabulate(wakeupCnt)(i => io.wakeUpPorts(i).bits.uop.pdest)
 
@@ -206,7 +207,7 @@ class IssueQueue(val fuTypeInt: BigInt, val wakeupCnt: Int, val bypassCnt: Int =
     val srcHitVec = List.tabulate(srcNum)(k =>
                       List.tabulate(iqSize)(i =>
                         List.tabulate(wakeupCnt)(j =>
-                          (prfSrc(k)(i) === cdbPdest(j)) && cdbValid(j))))
+                          (prfSrc(k)(i) === cdbPdest(j)) && (cdbValid(j) && cdbrfWen(i)))))
     val srcHit =  List.tabulate(srcNum)(k =>
                     List.tabulate(iqSize)(i =>
                       ParallelOR(srcHitVec(k)(i)).asBool()))
@@ -218,19 +219,26 @@ class IssueQueue(val fuTypeInt: BigInt, val wakeupCnt: Int, val bypassCnt: Int =
           // srcData(k)(i) := Mux1H(srcHitVec(k)(i), cdbData)
           srcData(k)(i) := ParallelMux(srcHitVec(k)(i) zip cdbData)
         }
+        XSDebug(srcHit(k)(i), "Wakeup: Sel:%d Src:%d|%d data:%x srcHitVec:%b cdbValid:%b cdbrfWen:%b\n", 
+          i.U, k.U, prfSrc(k)(i), ParallelMux(srcHitVec(k)(i) zip cdbData), VecInit(srcHitVec(k)(i)).asUInt, VecInit(cdbValid).asUInt, VecInit(cdbrfWen).asUInt)
+        for (j <- 0 until wakeupCnt) {
+          XSDebug(srcHitVec(k)(i)(j), "WakeUpHit: Sel:%d Src:%d|%d Wake:%d data:%x valid:%d rfWen:%d roqIdx:%x\n", i.U, k.U, prfSrc(k)(i), j.U, cdbData(j), cdbValid(j), cdbrfWen(j), io.wakeUpPorts(j).bits.uop.roqIdx)
+        }
       })
     }
+
     // From byPass [speculative] (just for ALU to listen to other ALU's res, include itself)
     // just need Tag(Ctrl). send out Tag when Tag is decided. other ALUIQ listen to them and decide Tag
     // byPassUops is one cycle before byPassDatas
     if (bypassCnt > 0) {
       val bypassPdest = List.tabulate(bypassCnt)(i => io.bypassUops(i).bits.pdest)
+      val bypassrfWen = List.tabulate(bypassCnt)(i => io.bypassUops(i).bits.ctrl.rfWen)
       val bypassValid = List.tabulate(bypassCnt)(i => io.bypassUops(i).valid) // may only need valid not fire()
       val bypassData = List.tabulate(bypassCnt)(i => io.bypassData(i).bits.data)
       val srcBpHitVec = List.tabulate(srcNum)(k =>
                           List.tabulate(iqSize)(i =>
                             List.tabulate(bypassCnt)(j =>
-                              (prfSrc(k)(i) === bypassPdest(j)) && bypassValid(j))))
+                              (prfSrc(k)(i) === bypassPdest(j)) && (bypassValid(j) && bypassrfWen(i)))))
       val srcBpHit =  List.tabulate(srcNum)(k =>
                         List.tabulate(iqSize)(i =>
                           ParallelOR(srcBpHitVec(k)(i)).asBool()))
@@ -254,9 +262,9 @@ class IssueQueue(val fuTypeInt: BigInt, val wakeupCnt: Int, val bypassCnt: Int =
 
       // Enqueue Bypass
       val enqBypass = WireInit(VecInit(false.B, false.B, false.B))
-      val enqBypassHitVec = List(List.tabulate(bypassCnt)(j => io.enqCtrl.bits.psrc1 === bypassPdest(j) && bypassValid(j) && io.enqCtrl.fire()),
-                                 List.tabulate(bypassCnt)(j => io.enqCtrl.bits.psrc2 === bypassPdest(j) && bypassValid(j) && io.enqCtrl.fire()),
-                                 List.tabulate(bypassCnt)(j => io.enqCtrl.bits.psrc3 === bypassPdest(j) && bypassValid(j) && io.enqCtrl.fire()))
+      val enqBypassHitVec = List(List.tabulate(bypassCnt)(j => io.enqCtrl.bits.psrc1 === bypassPdest(j) && bypassValid(j) && bypassrfWen(j) && io.enqCtrl.fire()),
+                                 List.tabulate(bypassCnt)(j => io.enqCtrl.bits.psrc2 === bypassPdest(j) && bypassValid(j) && bypassrfWen(j) && io.enqCtrl.fire()),
+                                 List.tabulate(bypassCnt)(j => io.enqCtrl.bits.psrc3 === bypassPdest(j) && bypassValid(j) && bypassrfWen(j) && io.enqCtrl.fire()))
       val enqBypassHitVecNext = enqBypassHitVec.map(i => i.map(j => RegNext(j)))
       enqBypass(0) := ParallelOR(enqBypassHitVec(0))
       enqBypass(1) := ParallelOR(enqBypassHitVec(1))

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -91,7 +91,7 @@ class Rename extends XSModule {
     val this_can_alloc = Mux(needIntDest, intCanAlloc, fpCanAlloc)
     io.in(i).ready := this_can_alloc && !isWalk
     last_can_alloc = last_can_alloc && this_can_alloc
-    uops(i).pdest := Mux(needIntDest, intFreeList.pdests(i), fpFreeList.pdests(i))
+    uops(i).pdest := Mux(needIntDest, intFreeList.pdests(i), Mux(uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen, 0.U, fpFreeList.pdests(i)))
     uops(i).freelistAllocPtr := Mux(needIntDest, intFreeList.allocPtrs(i), fpFreeList.allocPtrs(i))
 
     io.out(i).valid := io.in(i).fire()

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -75,10 +75,13 @@ class Roq(implicit val p: XSConfig) extends XSModule {
       writebacked(io.exeWbResults(i).bits.uop.roqIdx) := true.B
       exuData(io.exeWbResults(i).bits.uop.roqIdx) := io.exeWbResults(i).bits.data
       exuDebug(io.exeWbResults(i).bits.uop.roqIdx) := io.exeWbResults(i).bits.debug
-      XSInfo(io.exeWbResults(i).valid, "writebacked pc 0x%x wen %d data 0x%x\n", 
+      XSInfo(io.exeWbResults(i).valid, "writebacked pc 0x%x wen %d data 0x%x ldst %d pdst %d skip %x\n", 
         microOp(io.exeWbResults(i).bits.uop.roqIdx).cf.pc,
         microOp(io.exeWbResults(i).bits.uop.roqIdx).ctrl.rfWen, 
-        io.exeWbResults(i).bits.data
+        microOp(io.exeWbResults(i).bits.uop.roqIdx).ctrl.ldest, 
+        io.exeWbResults(i).bits.uop.pdest,
+        io.exeWbResults(i).bits.data,
+        io.exeWbResults(i).bits.debug.isMMIO
       )
     }
   }
@@ -86,8 +89,8 @@ class Roq(implicit val p: XSConfig) extends XSModule {
   // Commit uop to Rename
   val shouldWalkVec = Wire(Vec(CommitWidth, Bool()))
   shouldWalkVec(0) := ringBufferWalk =/= ringBufferWalkTarget
-  (1 until CommitWidth).map(i => shouldWalkVec(i) := (ringBufferWalk + i.U) =/= ringBufferWalkTarget && shouldWalkVec(i - 1))
-  val walkFinished = (0 until CommitWidth).map(i => (ringBufferWalk + i.U) === ringBufferWalkTarget).reduce(_||_) //FIXIT!!!!!!
+  (1 until CommitWidth).map(i => shouldWalkVec(i) := (ringBufferWalk - i.U) =/= ringBufferWalkTarget && shouldWalkVec(i - 1))
+  val walkFinished = (0 until CommitWidth).map(i => (ringBufferWalk - i.U) === ringBufferWalkTarget).reduce(_||_) //FIXIT!!!!!!
 
   for(i <- 0 until CommitWidth){
     when(state === s_idle){
@@ -110,12 +113,17 @@ class Roq(implicit val p: XSConfig) extends XSModule {
         microOp(ringBufferTail+i.U).cf.pc
       )
     }.otherwise{//state === s_walk
-      io.commits(i).valid := valid(ringBufferWalk+i.U) && shouldWalkVec(i)
-      io.commits(i).bits.uop := microOp(ringBufferWalk+i.U)
+      io.commits(i).valid := valid(ringBufferWalk-i.U) && shouldWalkVec(i)
+      io.commits(i).bits.uop := microOp(ringBufferWalk-i.U)
       when(shouldWalkVec(i)){
-        valid(ringBufferWalk+i.U) := false.B
+        valid(ringBufferWalk-i.U) := false.B
       }
-      XSInfo(io.commits(i).valid && shouldWalkVec(i), "walked pc %x wen %d ldst %d data %x\n", microOp(ringBufferTail+i.U).cf.pc, microOp(ringBufferTail+i.U).ctrl.rfWen, microOp(ringBufferTail+i.U).ctrl.ldest, exuData(ringBufferTail+i.U))
+      XSInfo(io.commits(i).valid && shouldWalkVec(i), "walked pc %x wen %d ldst %d data %x\n", 
+        microOp(ringBufferWalk-i.U).cf.pc, 
+        microOp(ringBufferWalk-i.U).ctrl.rfWen, 
+        microOp(ringBufferWalk-i.U).ctrl.ldest, 
+        exuData(ringBufferWalk-i.U)
+      )
     }
     io.commits(i).bits.isWalk := state === s_walk
   }
@@ -125,7 +133,7 @@ class Roq(implicit val p: XSConfig) extends XSModule {
     when(walkFinished) {
       state := s_idle
     }
-    ringBufferWalkExtended := ringBufferWalkExtended + CommitWidth.U
+    ringBufferWalkExtended := ringBufferWalkExtended - CommitWidth.U
     XSInfo("rolling back: head %d tail %d walk %d\n", ringBufferHead, ringBufferTail, ringBufferWalk)
   }
 
@@ -143,12 +151,11 @@ class Roq(implicit val p: XSConfig) extends XSModule {
   io.scommit := PopCount(validScommit.asUInt)
 
   // when redirect, walk back roq entries
-  val newHead = io.brqRedirect.bits.roqIdx + 1.U
   when(io.brqRedirect.valid){
     state := s_walk
-    ringBufferWalkExtended := newHead
-    ringBufferWalkTarget := ringBufferHeadExtended
-    ringBufferHeadExtended := newHead
+    ringBufferWalkExtended := ringBufferHeadExtended - 1.U
+    ringBufferWalkTarget := io.brqRedirect.bits.roqIdx
+    ringBufferHeadExtended := io.brqRedirect.bits.roqIdx + 1.U
   }
 
   // roq redirect only used for exception